LM3S308 Luminary Micro, Inc, LM3S308 Datasheet - Page 50

• Manufacturer Part Number: LM3S308
• Description: Lm3s308 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

JTAG Interface
5.4.1.8
5.4.2
5.4.2.1
5.4.2.2
5.4.2.3
50
BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 50 for
more information.
Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3 on page 50. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x1BA00477. This value indicates an ARM Cortex-M3, Version 1
processor. This allows the debuggers to automatically configure themselves to work correctly with
the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4 on page 50. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
Figure 5-4. BYPASS Register Format
Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 51. Each GPIO
pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
TDI
TDI
0
0
31
Version
TDO
28 27
Part Number
Preliminary
12 11
Manufacturer ID
1 0
1
TDO
June 04, 2008