LM3S308 Luminary Micro, Inc, LM3S308 Datasheet - Page 54

• Manufacturer Part Number: LM3S308
• Description: Lm3s308 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
6.1.2.5
54
The system provides a brown-out detection circuit that triggers if the power supply (V
below a brown-out threshold voltage (V
operation of logic and peripherals that operate off the power supply voltage (V
voltage. If a brown-out condition is detected, the system may generate a controller interrupt or a
system reset. The BOR circuit has a digital filter that protects against noise-related detection for the
interrupt condition. This feature may be optionally enabled.
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset sequence is as follows:
1.
2.
3.
4.
5.
The internal Brown-Out Reset timing is shown in Figure 19-11 on page 396.
Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 58). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1.
2.
3.
The software-initiated system reset timing is shown in Figure 19-12 on page 396.
When V
If the BORWT bit in the PBORCTL register is set and BORIOR is not set, the BOR condition is
resampled again, after a delay specified by BORTIM, to determine if the original condition was
caused by noise. If the BOR condition is not met the second time, then no further action is taken.
If the BOR condition exists, an internal reset is asserted.
The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
The internal BOR condition is reset after 500 µs to prevent another BOR condition from being
set before software has a chance to investigate the original cause.
A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
An internal reset is asserted.
The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
DD
drops below V
BTH
, an internal BOR condition is set.
Preliminary
BTH
). The circuit is provided to guard against improper
DD
) and not the LDO
June 04, 2008
DD
) drops