LM3S308 Luminary Micro, Inc, LM3S308 Datasheet - Page 90

• Manufacturer Part Number: LM3S308
• Description: Lm3s308 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
System Control
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
90
Bit/Field
31:17
15:10
9:8
16
RO
RO
31
15
0
0
RO
RO
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
30
14
0
0
MAXADCSPD
RO
RO
29
13
reserved
reserved
0
0
Name
reserved
ADC
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
RO
RO
RO
RO
26
10
0
0
R/W
RO
MAXADCSPD
Reset
25
0
9
0
0
0
0
0
reserved
Preliminary
R/W
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value
0x2
0x1
0x0
RO
RO
23
0
7
0
Description
500K samples/second
250K samples/second
125K samples/second
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
WDT
R/W
RO
19
0
3
0
RO
RO
18
0
2
0
reserved
RO
RO
17
0
1
0
June 04, 2008
ADC
R/W
RO
16
0
0
0