MT28F004B3VG-10 TET Micron, MT28F004B3VG-10 TET Datasheet - Page 10

• Manufacturer Part Number: MT28F004B3VG-10 TET
• Description: Flash Memory, 4Mbit, Sectored, 3.3V Supply, TSOP I, 40-Pin
• Manufacturer: Micron

INPUT OPERATIONS
array or to input a command to the CEL. A command
input issues an 8-bit command to the CEL to control the
mode of operation of the device. A WRITE is used to
input data to the memory array. The following section
describes both types of inputs. More information de-
scribing how to use the two types of inputs to write or
erase the device is provided in the Command Execution
section.
COMMANDS
and CE# and WE# must be LOW. Addresses are “Don’t
Care” but must be held stable, except during an ERASE
CONFIRM (described in a later section). The 8-bit com-
mand is input on DQ0-DQ7, while DQ8-DQ15 are
“Don’t Care” on the MT28F400B3. The command is
latched on the rising edge of CE# (CE#-controlled) or
WE# (WE#-controlled), whichever occurs first. The
condition of BYTE# on the MT28F400B3 has no effect
on a command input.
4Mb Smart 3 Boot Block Flash Memory
F45_1.p65 – Rev. 1/01
COMMAND
RESERVED
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP
ERASE CONFIRM/RESUME
WRITE SETUP
ERASE SUSPEND
The DQ pins are used either to input data to the
To perform a command input, OE# must be HIGH,
HEX CODE DESCRIPTION
40H or
D0H
90H
70H
20H
10H
B0H
00H
FFH
50H
The first command given in the two-cycle WRITE sequence. The write
data and address are given in the following cycle to complete the WRITE.
This command and all unlisted commands are invalid and should not
be called. These commands are reserved to allow for future feature
enhancements.
Must be issued after any other command cycle before the array can be
read. It is not necessary to issue this command after power-up or RESET.
Allows the device ID and manufacturer compatibility ID to be read. A0 is
used to decode between the manufacturer compatibility ID (A0 = LOW)
and device ID (A0 = HIGH).
Allows the status register to be read. Please refer to Table 2 for more
information on the status register bits.
Clears status register bits 3-5, which cannot be cleared by the ISM.
The first command given in the two-cycle ERASE sequence. The ERASE will
not be completed unless followed by ERASE CONFIRM.
The second command given in the two-cycle ERASE sequence. Must follow
an ERASE SETUP command to be valid. Also used during an ERASE
SUSPEND to resume the ERASE.
Requests a halt of the ERASE and puts the device into the erase suspend
mode. When the device is in this mode, only READ STATUS REGISTER,
READ ARRAY and ERASE RESUME commands may be executed.
Command Set
SMART 3 BOOT BLOCK FLASH MEMORY
Table 1
10
MEMORY ARRAY
lgic 0s but cannot change a given bit to a logic 1 from
a logic 0. Setting any bits to a logic 1 requires that the
entire block be erased. To perform a WRITE, OE# must
be HIGH, CE# and WE# must be LOW, and V
set to V
requires that the RP# pin be at V
A17/(A18) provide the address to be written, while the
data to be written to the array is input on the DQ pins.
The data and addresses are latched on the rising edge of
CE# (CE#-controlled) or WE# (WE#-controlled), which-
ever occurs first. A WRITE must be preceded by a WRITE
SETUP command. Details on how to input data to the
array will be covered in the Write Sequence section.
READs on the MT28F400B3. When BYTE# is LOW (byte
mode), data is input on DQ0-DQ7, DQ8-DQ14 are
High-Z and DQ15 becomes the lowest order address
input. When BYTE# is HIGH (word mode), data is input
on DQ0-DQ15.
A WRITE to the memory array sets the desired bits to
Selectable bus sizing applies to WRITEs as it does to
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PPH
1
or V
PPH
2
. Writing to the boot block also
HH
or WP# be HIGH. A0-
©2000, Micron Technology, Inc.
PP
4Mb
must be