MT28F004B3VG-10 TET Micron, MT28F004B3VG-10 TET Datasheet - Page 13

• Manufacturer Part Number: MT28F004B3VG-10 TET
• Description: Flash Memory, 4Mbit, Sectored, 3.3V Supply, TSOP I, 40-Pin
• Manufacturer: Micron

a null WRITE. To execute a null WRITE, FFH must be
written when BYTE# is LOW, or FFFFH must be written
when BYTE# is HIGH. Once the ISM status bit (SR7) has
been set, the device will be in the status register read
mode until another command is issued.
ERASE SEQUENCE
a block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a WRITE. To
provide added security against accidental block era-
sure, two consecutive command cycles are required to
initiate an ERASE of a block. In the first cycle, addresses
are “Don’t Care,” and ERASE SETUP (20H) is given. In
the second cycle, V
address within the block to be erased must be issued,
and ERASE CONFIRM (D0H) must be given. If a com-
mand other than ERASE CONFIRM is given, the write
and erase status bits (SR4 and SR5) will be set, and the
device will be in the status register read mode.
will start the ERASE of the addressed block. Any READ
operation will output the status register contents on
DQ0-DQ7. V
completed (SR7 = 1). Once the ERASE is completed, the
device will be in the status register read mode until
another command is issued. Erasing the boot block also
NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.
4Mb Smart 3 Boot Block Flash Memory
F45_1.p65 – Rev. 1/01
SR5
Executing an ERASE sequence will set all bits within
After the ERASE CONFIRM (D0H) is issued, the ISM
0
0
0
0
1
1
1
1
STATUS BITS
SR4
0
0
1
1
0
0
1
1
PP
must be held at V
SR3
PP
0
1
0
1
0
1
0
1
must be brought to V
ERROR DESCRIPTION
No errors
V
WRITE error
WRITE error, V
ERASE error
ERASE error, V
Command sequencing error or WRITE/ERASE error
Command sequencing error, V
PP
voltage error
PPH
until the ERASE is
Status Register Error Decode
PP
PP
voltage not valid at time of ERASE CONFIRM
voltage not valid at time of WRITE
PPH
SMART 3 BOOT BLOCK FLASH MEMORY
, an
Table 4
13
PP
requires that either the RP# pin be set to V
pin be held HIGH at the same time V
ERASE SUSPENSION
ERASE is in progress is ERASE SUSPEND. This command
allows other commands to be executed while pausing
the ERASE in progress. Once the device has reached the
erase suspend mode, the erase suspend status bit (SR6)
and ISM status bit (SR7) will be set. The device may now
be given a READ ARRAY, ERASE RESUME or READ
STATUS REGISTER command. After READ ARRAY has
been issued, any location not within the block being
erased may be read. If ERASE RESUME is issued before
SR6 has been set, the device will immediately proceed
with the ERASE in progress.
ERROR HANDLING
(SR3), write (SR4) and erase (SR5) status bits may be
checked. If one or a combination of these three bits has
been set, an error has occurred. The ISM cannot reset
these three bits. To clear these bits, CLEAR STATUS
REGISTER (50H) must be given. If the V
(SR3) is set, further WRITE or ERASE operations cannot
resume until the status register is cleared. Table 4 lists
the combination of errors.
voltage error, with WRITE and ERASE errors
The only command that may be issued while an
After the ISM status bit (SR7) has been set, the V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
PP
©2000, Micron Technology, Inc.
is set to V
HH
PP
or the WP#
status bit
4Mb
PPH
PP
.