MT28F004B3VG-10 TET Micron, MT28F004B3VG-10 TET Datasheet - Page 8

• Manufacturer Part Number: MT28F004B3VG-10 TET
• Description: Flash Memory, 4Mbit, Sectored, 3.3V Supply, TSOP I, 40-Pin
• Manufacturer: Micron

COMMAND EXECUTION LOGIC (CEL)
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register or
status register). Commands may be issued to the CEL
while the ISM is active. However, there are restrictions
on what commands are allowed in this condition. See
the Command Execution section for more detail.
DEEP POWER-DOWN MODE
MT28F004B3 and MT28F400B3 feature a very low cur-
rent, deep power-down mode. To enter this mode, the
RP# pin is taken to V
draw is a maximum of 8µA at 3.3V V
power-down also clears the status register and sets the
ISM to the read array mode.
MEMORY ARCHITECTURE
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into seven addressable blocks that vary in size
and are independently erasable. When blocks rather
4Mb Smart 3 Boot Block Flash Memory
F45_1.p65 – Rev. 1/01
The CEL receives and interprets commands to the
To allow for maximum power conservation, the
The MT28F004B3 and MT28F400B3 memory array
WORD ADDRESS
MT28F004B3/400B3xx-xxB
30000H
20000H
10000H
04000H
03000H
02000H
00000H
03FFFH
02FFFH
01FFFH
3FFFFH
2FFFFH
1FFFFH
0FFFFH
Bottom Boot
BYTE ADDRESS
SS
60000H
40000H
20000H
08000H
06000H
04000H
00000H
7FFFFH
5FFFFH
3FFFFH
1FFFFH
07FFFH
05FFFH
03FFFH
±0.2V. In this mode, the current
8KB Parameter Block
8KB Parameter Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
16KB Boot Block
CC
. Entering deep
Memory Address Maps
SMART 3 BOOT BLOCK FLASH MEMORY
Figure 1
8
than the entire array are erased, total device endurance
is enhanced, as is system flexibility. Only the ERASE
function is block-oriented. All READ and WRITE opera-
tions are done on a random-access basis.
ERASE or WRITE with a hardware protection circuit
which requires that a super-voltage be applied to RP# or
that the WP# pin be driven HIGH before erasure is
commenced. The boot block is intended for the core
firmware required for basic system functionality. The
remaining six blocks do not require either of these two
conditions be met before WRITE or ERASE operations.
BOOT BLOCK
security for the most sensitive portions of the firmware.
This 16KB block may only be erased or written when the
RP# pin is at the specified boot block unlock voltage
(V
WRITE or ERASE of the boot block, the RP# pin must be
held at V
or WRITE is completed. The V
(3.3V or 5V) when the boot block is written to or erased.
HH
The boot block is protected from unintentional
The hardware-protected boot block provides extra
) of 12V or when the WP# pin is V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WORD ADDRESS
HH
MT28F004B3/400B3xx-xxT
3D000H
3C000H
3E000H
3DFFFH
30000H
20000H
10000H
00000H
3CFFFH
3BFFFH
3FFFFH
2FFFFH
1FFFFH
0FFFFH
or the WP# pin held HIGH until the ERASE
BYTE ADDRESS
Top Boot
7A000H
7C000H
78000H
60000H
40000H
20000H
00000H
7BFFFH
79FFFH
77FFFH
7FFFFH
5FFFFH
3FFFFH
1FFFFH
8KB Parameter Block
8KB Parameter Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
16KB Boot Block
PP
pin must be at V
©2000, Micron Technology, Inc.
IH
. During a
4Mb
PPH