MT28F004B3VG-10TET Micron, MT28F004B3VG-10TET Datasheet - Page 4

• Manufacturer Part Number: MT28F004B3VG-10TET
• Description: 4Mb SMART 3 BOOT BLOCK FLASH MEMORY
• Manufacturer: Micron

PIN DESCRIPTIONS
4Mb Smart 3 Boot Block Flash Memory
F45_2.p65 – Rev. 2, Pub. 3/01
36, 35, 34, 3 2, 1, 40, 13
11, 10, 9, 8, 21, 20, 19,
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
42, 41, 40, 15, 14, 8, 7, 19, 18, 8, 7,
39, 38, 37, 36, 6, 5, 4, 3, 6, 5, 4, 3, 2,
15, 17, 19, 25-28, 32-35 29, 31, 33, DQ0–DQ7
21, 24, 26,
16, 18, 20,
22, 25, 27,
NUMBERS
7, 6, 5, 4,
28, 30
13, 32
43
12
44
14
33
31
23
29
2
1
–
18, 17, 16,
NUMBERS
29, 37, 38 9, 10, 15, 16
30, 31
23, 39
12
22
10
24
11
9
–
–
–
25, 24, 23,
22, 21, 20,
35, 38, 40,
30, 32, 34, DQ8–DQ14
NUMBERS
36, 39, 41,
1, 48, 17
42, 44
27, 46
11
14
26
12
28
47
45
43
13
37
SYMBOL
A0–A17/
BYTE#
DQ15/
(A18)
(A-1)
WE#
WP#
OE#
CE#
RP#
V
V
V
NC
CC
PP
SS
SMART 3 BOOT BLOCK FLASH MEMORY
Output Input: LSB of address input when BYTE# = LOW during
Output or data input pins during a WRITE. These pins are used
Output or data input pins during a WRITE when BYTE# = HIGH.
Supply Write/Erase Supply Voltage: From a WRITE or ERASE
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
Input/ Data I/O: MSB of data when BYTE# = HIGH. Address
Input/ Data I/Os: Data output pins during any READ operation
Input/ Data I/Os: Data output pins during any READ operation
Input Write Enable: Determines if a given cycle is a WRITE
Input Write Protect: Unlocks the boot block when HIGH if V
Input Chip Enable: Activates the device when LOW. When
Input Reset/Power-Down: When LOW, RP# clears the status
Input Output Enable: Enables data output buffers when
Input Byte Enable: If BYTE# = HIGH, the upper byte is active
Input Address Inputs: Select a unique, 16-bit word or 8-bit
TYPE
–
4
cycle. If WE# is LOW, the cycle is either a WRITE to the
command execution logic (CEL) or to the memory array.
= V
WRITE or ERASE. Does not affect WRITE or ERASE
operation on other blocks.
CE# is HIGH, the device is disabled and goes into
standby power mode.
register, sets the internal state machine (ISM) to the
array read mode and places the device in deep power-
down mode. All inputs, including CE#, are “Don’t
Care,” and all outputs are High-Z. RP# unlocks the boot
block and overrides the condition of WP# when at V
(12V), and must be held at V
of operation.
LOW. When OE# is HIGH, the output buffers are
disabled.
through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are
High-Z, and all data is accessed through DQ0–DQ7.
DQ15/(A-1) becomes the least significant address input.
byte. The DQ15/(A-1) input becomes the lowest order
address when BYTE# = LOW (MT28F400B3) to allow for
a selection of an 8-bit byte from the 524,288 available.
READ or WRITE operation.
to inputcommands to the CEL.
These pins are High-Z when BYTE# is LOW.
CONFIRM until completion of the WRITE or ERASE, V
must be at V
during all other operations.
unconnected.
No Connect: These pins may be driven or left
PPH
1
(3.3V) or V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PPH
1
(3.3V) or V
PPH
2
DESCRIPTION
(5V) and RP# = V
PPH
IH
2
during all other modes
(5V). V
PP
IH
©2001, Micron Technology, Inc.
= “Don’t Care”
during a
4Mb
HH
PP
PP