MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet
MT9074AL
Manufacturer Part Number
MT9074AL
Description
T1/E1/J1 Single Chip Transceiver
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT9074AL.pdf
(124 pages)
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Features
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Applications
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R/W/WR
D7~D0
DS/RD
Combined E1 (PCM30) and T1 (D4/ESF) framer,
Line Interface Unit (LIU) and link controller with
optional digital framer only mode
In T1 mode the LIU can recover signals attenuated
by up to 30 dB (5000 ft. of 24 AWG cable)
In E1 mode the LIU can recover signals attenuated
by up to 30 dB (1900 m. of 0.65mm cable)
Two HDLCs: FDL and channel 24 in T1 mode,
timeslot 0 (Sa bits) and timeslot 16 in E1 mode
Two-frame elastic buffer in Rx & Tx (T1) directions
Programmable transmit delay through transmit slip
buffer
Low jitter DPLL for clock generation
Enhanced alarms, performance monitoring and
error insertion functions
Intel or Motorola non-multiplexed parallel
microprocessor interface
ST-BUS 2.048 Mbit/s backplane bus for both data
and signaling
Japan Telecom J1 Framing and Yellow Alarm
Hardware data link access
JTAG Boundary Scan
E1/T1 add/drop multiplexers and channel banks
CO and PBX equipment interfaces
Primary Rate ISDN nodes
Digital Cross-connect Systems (DCS)
DSTo
CSTo
DSTi
CSTi
Tms
AC0
AC4
Tclk
IRQ
Tdo
Tdi
Trst
CS
Interface
Interface
ST-BUS
ST-BUS
ST Loop
RxDLCLK RxDL
TxDL TxDLCLK
Data Link,
HDLC0
HDLC1
Figure 1 - Functional Block Diagram
PL Loop
Receive Framing, Performance Monitoring,
RxMF
Test Signal Generation and Slip Buffer
Alarm Detection, 2 Frame Slip Buffer
TxMF
Transmit Framing, Error,
Bit Buffer
LOS
National
Buffer
CAS
DS5024
Description
The MT9074 is a single chip device, operable in
either T1 or E1 mode, integrating either an advanced
T1 (T1 mode) or PCM30 (E1 mode) framer with a
Line Interface Unit (LIU).
The framer interfaces to a 2.048 Mbit/s backplane
providing selectable data link access with optional
HDLC controllers for either the FDL bits and channel
24 (T1 mode) or S
The LIU interfaces the framer to T1 (T1 mode) or
PCM30 (E1 mode) transformer-isolated four-wire line
with minimal external components required.
*
confirm that the installed chip is the most recent revision of
MT9074A as follows:
1.
2.
MT9074A was revised after its market introduction. Software can
In T1 mode, the LSB (Least Significant Bit) of the
Synchronization Status Word - bit 0, Page 3 Address 10H is set
high.
Batch codes 61755.0 or higher, and/or date code beginning
with 00, 01, 02, etc.
T1/E1/J1 Single Chip Transceiver
RxFP
MT9074AP
MT9074AL
TxAO TxB TxA
DG Loop
Ordering Information *
Jitter Attenuator
& Clock Control
a
E1.5o
-40°C to 85°C
bits and channel 16 (E1 mode).
68 Pin PLCC
100 Pin MQFP
ISSUE 7
F0b C4b
Driver
Line
Data Sheet
MT9074
September 2002
S/FR
TTIP
TRING
BS/LS
OSC1
OSC2
RTIP
RRING
1
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