MT90820AL1 Zarlink Semiconductor, Inc., MT90820AL1 Datasheet
MT90820AL1
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MT90820AL1 Summary of contents
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... FE/ WFPS HCLK Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved. CMOS ST-BUS MT90820AP MT90820AL MT90820APR MT90820AL1 MT90820AP1 MT90820APR1 Applications • Medium and large switching platforms • CTI application • Voice/data multiplexer • ...
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Description The MT90820 Large Digital Switch has a non-blocking switch capacity of 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s, 1,024 x 1,024 channels at 4.096 Mb/s and 512 x 512 channels at 2.048 Mb/s. The ...
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STi0 STi1 13 STi2 STi3 15 STi4 STi5 17 STi6 STi7 19 STi8 STi9 21 STi10 STi11 23 STi12 STi13 25 STi14 STi15 27 F0i FE/HCLK 29 VSS CLK 31 VDD ...
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Pin Description Pin # Name 84 100 PLCC MQFP 1, 11, 31, 41, V Ground. SS 30, 54 56, 66, 64 32 Volt Power Supply 68-75 ...
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Pin Description Pin # Name 84 100 PLCC MQFP 39 12 RESET Device Reset (Schmitt Trigger Input): This input (active LOW) puts the MT90820 in its reset state that clears the device internal counters, registers and brings STo0 - 15 ...
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Pin Description Pin # Name 84 100 PLCC MQFP 76 57 ODE Output Drive Enable (Input): This is the output enable control for the STo0 to STo15 serial outputs. When ODE input is low and the OSB bit of the ...
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Data to be output on the serial streams may come from either the data memory or connection memory. Locations in the connection memory are associated with particular ST-BUS output channels. When a channel is due to be transmitted on an ...
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Wide Frame Pulse (WFP) Frame Alignment Timing When the device is in WFP frame alignment mode, the CLK input must be at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 kHz frame pulse is in ST-BUS format. ...
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Input Frame Offset Selection Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e., F0i). This feature is useful in compensating for variable path delays caused ...
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In wideband data applications, select constant throughput delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the type of throughput delay selected in ...
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The microprocessor interface automatically identifies the type of micro-processor bus connected to the MT90820. This circuit uses the level of the DS/RD input pin at the rising edge of AS/ALE to identify the appropriate bus timing connected to the MT90820. ...
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CSTo pin. The contents of the CSTo bit in position 32 (STo1, CH0) of the connection memory is output on the second clock cycle of channel 31 via CSTo pin. If the ODE pin or ...
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(Note ...
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Read/Write Address: 00 Reset Value: 0000 Bit Name STA3-0 Stream Address Bits. The binary value expressed by these bits refers to the input or output data stream, ...
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Read/Write Address: 01 Reset Value: 0000 Bit Name 3 OSB Output Stand By. When ODE = 0 and OSB = 0, the output drivers of STo0 to STo15 are in ...
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Read Address: 02 Reset Value: 0000 CFE FD11 0 Bit Name FD10-0 Frame Delay Bits. The binary value expressed in these bits refers to the measured input offset value. These ...
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Read/Write Address Reset value: 0000 OF32 OF31 OF30 DLE3 OF22 OF72 OF71 OF70 DLE7 OF62 OF112 OF111 OF110 DLE11 OF102 15 ...
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Input Stream Offset + 0.5 clock period shift +1.0 clock period shift +1.5 clock period shift +2.0 clock period shift +2.5 clock period shift +3.0 clock period shift +3.5 clock period shift +4.0 clock period shift +4.5 clock period shift ...
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V/C MC CSTo OE LPBK Bit Name 15 LPBK 14 V CSTo SAB3-0 7 (Note CAB6-0 (Note 1) Note 1: If bit 13 ...
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Test Access Port (TAP) The Test Access Port (TAP) provides access to the many test functions of the MT90820. It consists of three input pins and one output pin. The following pins are from the TAP. • Test Clock Input ...
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MT90820 Boundary Scan Bit 0 to Bit 117 Device Pin Tristate Output Control Scan Cell STo7 0 1 STo6 2 3 STo5 4 5 STo4 6 7 STo3 8 9 STo2 10 11 STo1 12 13 STo0 14 15 ODE ...
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Device Pin FE/HCLK Applications Switch Matrix Architectures The MT90820 is an ideal device for medium to large size switch matrices. Applications where voice and grouped data channels are transported within the same frame, the voice samples have to be time ...
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Serial Input Frame Alignment Evaluation The MT90820 is capable of performing frame alignment evaluation. The frame pulse under evaluation is connected to the FE (frame measurement) pin. An external multiplexer is required to selected one of the frame pulses related ...
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The MT90820 is designed to accept a common frame pulse F0i, the 4.096 MHz and 16.384 MHz clocks required by the HMVIP standards. To enable the Width Frame Pulse Frame Alignment Mode, the WFPS pin has to be set to ...
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Streams 4,096 x 4,096 Switch Matrix (Figure Streams 4,096 x 4,096 Switch Matrix (Figure 5) Figure 8 - 8,192 x 8,192 Channel Switch Matrix DSTo E1 E1/T1 Trunk 0 DSTi 0 DSTo E1 E1/T1 Trunk 1 ...
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Recommended Operating Conditions - Characteristics 1 Operating Temperature 2 Positive Supply 3 Input High Voltage 4 Input Low Voltage DC Electrical Characteristics - Voltages are with respect to ground (V Characteristics Mb/s Supply Current @ 4 Mb/s ...
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AC Electrical Characteristics - Frame Pulse and CLK Characteristic 1 Frame pulse width (ST-BUS, GCI) Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s 2 Frame Pulse Setup time before CLK falling (ST-BUS or ...
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AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes Characteristic 1 Sti Set-up Time 2 Sti Hold Time 3 Sto Delay - Active to Active @ 2.048 Mb/s mode @ 4.096 Mb/s mode @ 8.192 Mb/s mode @ ...
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FPW F0i t t FPS FPH CLK t SOD STo Bit 0, Last Ch (Note1) STi Bit 0, Last Ch (Note1) Note 1: 2.048 Mb/s mode, last channel = ch 31, 4.196 Mb/s mode, last channel = ch 63, ...
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F0i HCLK 4.096MHz CLK 16.384MHz STo Bit 1, Ch 127 STi Bit 1, Ch 127 Figure 12 - WFP Bus Timing for High Speed Serial Interface (8.192Mb/s), when WFPS pin = 1 Note 1: High Impedance is measured by pulling ...
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AC Electrical Characteristics - Multiplexed Bus Timing (Mode 1) Characteristics 1 ALE pulse width 2 Address setup from ALE falling 3 Address hold from ALE falling 4 RD active after ALE falling 5 Data setup from DTA Low on Read ...
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ALW ALE t ADS AD0-AD7 HiZ D8-D15 DTA AC Electrical Characteristics - Multiplexed Bus Timing (Mode 2) Characteristics 1 AS pulse width 2 Address setup from AS falling 3 Address hold from AS falling 4 Data ...
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DS R/W AS AD0-AD7 HiZ D8-D15 WR AD0-AD7 D8-D15 HiZ RD CS DTA AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling ...
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DS CS R/W A0-A7 AD0-AD7 D8-D15 READ AD0-AD7 D8-D15 WRITE DTA Figure 17 - Motorola Non-Multiplexed Bus Timing MT90820 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t t DSW SWD VALID WRITE DATA t DDR t ...
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