MT8889C

Manufacturer Part NumberMT8889C
DescriptionIntegrated DTMFTransceiver with Adaptive Micro Interface
ManufacturerMitel Semiconductor
MT8889C datasheet
 


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Features
Central office quality DTMF transmitter/
receiver
Low power consumption
High speed adaptive micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30dBm
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Description
The MT8889C is a monolithic DTMF transceiver with
call progress filter.
It is fabricated in CMOS
technology offering low power consumption and high
reliability.
D/A
TONE
Converters
Tone Burst
Control
Gating Cct.
Logic
IN+
+
Dial
Tone
-
High Group
IN-
Filter
Filter
GS
Low Group
OSC1
Filter
Oscillator
Circuit
OSC2
Control
Bias
Circuit
V
V
V
DD
Ref
SS
with Adaptive Micro Interface
MT8889CE/CE-1
MT8889CC/CC-1
MT8889CS/CS-1
MT8889CN/CN-1
The receiver section is based upon the industry
standard
transmitter
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT8889C utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT8889C-1 is functionally identical to the
MT8889C except the receiver is enhanced to accept
lower level signals, and also has a specified low
signal rejection level.
Row and
Transmit Data
Column
Register
Counters
Status
Register
Control
Register
A
Digital
Algorithm
Control
and Code
Converter
Register
B
Receive Data
Steering
Logic
Register
Logic
ESt
St/GT
Figure 1 - Functional Block Diagram
MT8889C/MT8889C-1
Integrated DTMF Transceiver
ISSUE 2
Ordering Information
20 Pin Plastic DIP
20 Pin Ceramic DIP
20 Pin SOIC
24 Pin SSOP
-40°C to +85°C
MT8870
DTMF
receiver
while
utilizes
a
switched
capacitor
Data
Bus
Buffer
Interrupt
Logic
I/O
Control
May 1995
the
D/A
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0
4-107

MT8889C Summary of contents

  • Page 1

    ... Credit card systems • Paging systems • Repeater systems/mobile radio • Interconnect dialers • Personal computers Description The MT8889C is a monolithic DTMF transceiver with call progress filter fabricated in CMOS technology offering low power consumption and high reliability. D/A TONE Converters Tone Burst Control Gating Cct ...

  • Page 2

    ... MT8889C/MT8889C IN IN VRef VSS 15 OSC1 6 14 OSC2 7 13 TONE 8 12 R/W/ PIN CERDIP/PLASTIC DIP/SOIC Pin Description Pin # Name IN+ Non-inverting op-amp input IN- Inverting op-amp input Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor ...

  • Page 3

    ... The adaptive micro interface allows microcontrollers, such as the 68HC11, 80C51 and TMS370C50, to access the MT8889C/MT8889C-1 internal registers. Input Configuration The input arrangement of the MT8889C/MT8889C-1 provides a differential-input operational amplifier as well as a bias source (V ), which is used to bias the Ref inputs ...

  • Page 4

    ... V DD MT8889C/ MT8889C-1 V St/GT ESt Guard Time Adjustment The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7): ...

  • Page 5

    ... Figure 7 with a description of the events in Figure 9. Call Progress Filter A call progress mode, using MT8889C-1, can be selected allowing the detection of various tones, which identify the progress of a telephone call on the network. tone input and DTMF input are common, however, call progress tones can only be detected when CP EVENTS A ...

  • Page 6

    ... GUARD TIME, TONE ABSENT. GTA DTMF Generator The DTMF transmitter employed in the MT8889C/ MT8889C-1 is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters ...

  • Page 7

    ... Table 2. Actual Frequencies Versus Standard Distortion Calculations The MT8889C/MT8889C-1 is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The internal summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize intermodulation distortion for a single tone can be calculated using ...

  • Page 8

    ... Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro- controllers with multiplexed address and data buses. MT8889C/ MT8889C-1 The MT8889C/MT8889C-1 latches in the state of RD OSC1 OSC2 on the falling edge of CS. When RD is high, Intel processor operation is selected. address latch enable (ALE) output with the high-byte address (P2) decode output, CS can be generated ...

  • Page 9

    ... Write to Transmit Data Register 1 0 Read from Receive Data Register 0 1 Write to Control Register 1 0 Read from Status Register IRQ CP/DTMF TOUT Table 4. CRA Bit Positions S/D TEST BURST ENABLE Table 5. CRB Bit Positions MT8889C/MT8889C-1 CS D0-D3 RS0 DS/RD R/W/WR MT8889C/MT8889C-1 CS D0-D3 RS0 DS/RD R/W/WR (b) 4-115 ...

  • Page 10

    ... MT8889C/MT8889C-1 BIT NAME b0 TOUT Tone Output Control. A logic high enables the tone output; a logic low turns the tone output off. This bit controls all transmit tone functions. b1 CP/DTMF Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode; ...

  • Page 11

    ... RS0 CS * Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT8889C/MT8889C-1 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. STATUS FLAG CLEARED Interrupt is inactive ...

  • Page 12

    ... MT8889C/MT8889C-1 MMD6150 (or equivalent) TEST POINT 130 Test load for D0-D3 pins A software reset must be included at the beginning of all programs to initialize the control registers after power up. The initialization procedure should be implemented 100ms after power up. Description: 1) Read Status Register 2) Write to Control Register 3) Write to Control Register ...

  • Page 13

    ... OHO 2.4 2.5 Ref -1.4 -6 2.0 4 -0.5 -3 MT8889C/MT8889C-1 Min Max 6 V -0 -65 +150 1000 Max Units Test Conditions 5.25 V +85 °C MHz Max Units Test Conditions 5. 57 Note 9* 1.5 V Note 9* 2 =5V ...

  • Page 14

    ... Valid input signal levels (each tone of composite signal Input Signal Level Reject † Characteristics are over recommended temperature and at V MT8889C AC Electrical Characteristics Characteristics Valid input signal levels R 1 (each tone of composite X signal) † Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13. ...

  • Page 15

    ... LOUT THD -35 f ±0 3.5759 3.5795 3.5831 C t CLRF MT8889C/MT8889C-1 ), unless otherwise stated. SS Max Units Conditions 500 Hz @ -25 dBm, Note -25 dBm Hz @ -25 dBm dBm Max Units Conditions unless otherwise stated. Max ...

  • Page 16

    ... MT8889C/MT8889C-1 AC Electrical Characteristics Characteristics 1 DS/RD/WR clock frequency 2 DS/RD/WR cycle period 3 DS/RD/WR low pulse width 4 DS/RD/WR high pulse width 5 DS/RD/WR rise and fall time 6 R/W setup time 7 R/W hold time 8 Address setup time (RS0) 9 Address hold time (RS0) 10 Data hold time (read) 11 DS/RD to valid data delay (read) 12 Data setup time (write) ...

  • Page 17

    ... RWS 16 bytes of Addr t CSS CSS is from DS rising edge to CS rising edge t RWS t DDR AS Addr Addr CSH High Byte of Addr t CSS MT8889C/MT8889C-1 t RWH t DDR t DHR t t DSW DHW t CSH CSH t RWH t DHR Data Data t t DSW DHW ...

  • Page 18

    ... MT8889C/MT8889C-1 ALE P0* A0-A7 (RS0, D0-D3 (Addr ALE.Addr * microprocessor pins Figure 19 - 8031/8051/8085 Read Timing Diagram ALE P0* (RS0, D0-D3 (Addr ALE.Addr * microprocessor pins Figure 20 - 8031/8051/8085 Write Timing Diagram 4-124 t CSS t t DDR AH A8-A15 Address t CSH t CSS t DSW t AH A0-A7 Data A8-A15 Address t CSH ...