MT8889C Mitel Semiconductor, MT8889C Datasheet - Page 9

• Manufacturer Part Number: MT8889C
• Description: Integrated DTMFTransceiver with Adaptive Micro Interface
• Manufacturer: Mitel Semiconductor

The adaptive micro interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last
valid DTMF digit received. Data entered into the
write-only Transmit Data Register will determine
which tone pair is to be generated (see Table 1 for
coding details). Transceiver control is accomplished
with two control registers (see Tables 6 and 7), CRA
and CRB, which have the same address. A write
operation to CRB is executed by first setting the
most significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).
A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 15). Refer to
Tables 4-7 for bit descriptions of the two control
registers.
The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).
MC6800/6802
MC6809
A0-A15
A0-A15
D0-D3
D0-D3
VMA
R/W
RW
Figure 12 a) & b) - MT8889 Interface Connections for Various Intel and Motorola Micros
Q
E
2
(a)
MT8889/MT8889C-1
MT8889/MT8889C-1
CS
RS0
D0-D3
R/W/WR
DS/RD
CS
RS0
D0-D3
R/W/WR
DS/RD
RS0
MC68HC11
8031/8051
8080/8085
0
0
1
1
RSEL
AD0-AD3
C/R
b3
b3
A8-A15
A8-A15
ALE
Motorola
WR
Table 3. Internal Register Functions
RW
RD
DS
AS
P0
R/W
0
1
0
1
MT8889C/MT8889C-1
Table 4. CRA Bit Positions
Table 5. CRB Bit Positions
S/D
IRQ
b2
b2
WR
0
1
0
1
Intel
(b)
RD
1
0
1
0
CP/DTMF
TEST
Write to Transmit
Data Register
Read from Receive
Data Register
Write to Control Register
Read from Status Register
MT8889C/MT8889C-1
MT8889C/MT8889C-1
b1
b1
CS
D0-D3
RS0
DS/RD
R/W/WR
CS
D0-D3
RS0
DS/RD
R/W/WR
FUNCTION
ENABLE
BURST
TOUT
b0
b0
4-115