MT8889 Zarlink Semiconductor, Inc., MT8889 Datasheet - Page 2

• Manufacturer Part Number: MT8889
• Description: Integrated DTMF Transceiver with Adaptive Micro Interface
• Manufacturer: Zarlink Semiconductor, Inc.

MT8889C
Pin Description
2
14-
20
10
11
12
13
17
18
19
20
1
2
3
4
5
6
7
8
9
Pin #
8, 9,
16,17
18-21
24
10
11
12
13
14
15
22
23
24
1
2
3
4
5
6
7
R/W/WR
TONE
OSC1
OSC2
VRef
VSS
IN+
GS
CS
IN-
20 PIN PLASTIC DIP/SOIC
Name
D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
OSC1 DTMF clock/oscillator input. Connect a 4.7M
OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
TONE Output from internal DTMF transmitter.
St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V
( WR )
( RD)
V
R/W
RS0
IRQ/
V
V
IN+
ESt
GS
NC
IN-
CS
DS
CP
Ref
DD
SS
10
1
2
3
4
5
6
7
8
9
Non-inverting op-amp input.
Inverting op-amp input.
Gain Select . Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage output (V
Ground (0V).
used.
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
(Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible.
Chip Select input. This signal must be qualified externally by either address strobe (AS),
valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
(Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only
required when the device is being accessed. TTL compatible.
Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
(Intel). TTL compatible.
Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
Positive power supply (5V typical).
No Connection.
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
TSt
Figure 2 - Pin Connections
frees the device to accept a new tone pair. The GT output acts to
DD
/2).
Description
R/W/WR
OSC1
OSC2
TONE
VRef
VSS
IN+
Ω
GS
NC
NC
CS
IN-
resistor to VSS if crystal oscillator is
10
11
12
1
2
3
4
5
6
7
8
9
24 PIN SSOP
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
TSt
detected at