MT8889CC_CC-1

Manufacturer Part NumberMT8889CC_CC-1
Description6V 10mA integrated DTMF transceiver with adaptive micro interface. For paging systems, repeater systems/mobile radio, credit card systems, personal computers, interconnect dialers
ManufacturerMitel Semiconductor
MT8889CC_CC-1 datasheet
 


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MT8889C/MT8889C-1
MMD6150 (or
equivalent)
TEST POINT
130 pF
24 k
Test load for D0-D3 pins
A software reset must be included at the beginning of all programs to initialize the control registers after
power up. The initialization procedure should be implemented 100ms after power up.
Description:
1) Read Status Register
2) Write to Control Register
3) Write to Control Register
4) Write to Control Register
5) Write to Control Register
6) Read Status Register
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS
Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence:
1) Write to Control Register A
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B
(burst mode)
3) Write to Transmit Data Register
(send a digit 7)
4) Wait for an Interrupt or Poll Status Register
5) Read the Status Register
-if bit 1 is set, the Tx is ready for the next tone, in which case ...
Write to Transmit Register
(send a digit 5)
-if bit 2 is set, a DTMF tone has been received, in which case ....
Read the Receive Data Register
-if both bits are set ...
Read the Receive Data Register
Write to Transmit Data Register
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( ±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)
4-118
5.0 VDC
2.4 k
TEST POINT
MMD7000 (or
equivalent)
Figure 14 - Test Circuits
INITIALIZATION PROCEDURE
Motorola
Intel
RS0
R/W
WR RD
1
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
RS0
R/W
WR RD
1
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
0
0
Figure 15 - Application Notes
5.0 VDC
3 k
100 pF
Test load for IRQ/CP pin
Data
b3
b2
b1
b0
0
X
X
X
X
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
X
X
X
X
b3
b2
b1
b0
1
1
1
0
1
1
0
0
0
0
1
0
1
1
1
0
X
X
X
X
1
0
1
0
1
0
X
X
X
X
0
X
X
X
X
1
0
1
0
1