MT8889CC_CC-1

Manufacturer Part NumberMT8889CC_CC-1
Description6V 10mA integrated DTMF transceiver with adaptive micro interface. For paging systems, repeater systems/mobile radio, credit card systems, personal computers, interconnect dialers
ManufacturerMitel Semiconductor
MT8889CC_CC-1 datasheet
 


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MT8889C/MT8889C-1
20
1
IN+
2
19
IN-
18
3
GS
17
VRef
4
5
16
VSS
15
OSC1
6
14
OSC2
7
13
TONE
8
12
R/W/WR
9
11
CS
10
20 PIN CERDIP/PLASTIC DIP/SOIC
Pin Description
Pin #
Name
20
24
1
1
IN+
Non-inverting op-amp input.
2
2
IN-
Inverting op-amp input.
3
3
GS
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
4
V
Reference Voltage output (V
Ref
5
5
V
Ground (0V).
SS
6
6
OSC1
Oscillator input. This pin can also be driven directly by an external clock.
7
7
OSC2
Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
8
10
TONE
Output from internal DTMF transmitter.
9
11
R/W
(Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible.
(WR)
10
12
CS
Chip Select input. This signal must be qualified externally by either address strobe (AS),
valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
11
13
RS0
Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
12
14 DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only
required when the device is being accessed. TTL compatible.
13
15
IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
14-
18-
D0-D3
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
17
21
(Intel). TTL compatible.
18
22
ESt
Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
19
23
St/GT
Steering Input/Guard Time output (bidirectional). A voltage greater than V
St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
20
24
V
Positive power supply (5V typ.).
DD
8,9
NC
No Connection.
16,
17
4-108
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
Figure 2 - Pin Connections
Description
/2).
DD
frees the device to accept a new tone pair. The GT output acts to
TSt
24
IN+
1
VDD
2
23
IN-
St/GT
22
3
GS
ESt
21
4
D3
VRef
5
20
D2
VSS
19
6
D1
OSC1
18
OSC2
7
D0
17
NC
8
NC
16
NC
9
NC
TONE
15
10
IRQ/CP
14
R/W/WR
11
DS/RD
13
12
CS
RS0
24 PIN SSOP
detected at
TSt