MT8889CN Zarlink Semiconductor, Inc., MT8889CN Datasheet - Page 12

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MT8889CN

Manufacturer Part Number
MT8889CN
Description
Integrated DTMF Transceiver with Adaptive Micro Interface
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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The MT8889C design incorporates an adaptive interface, which allows it to be connected to various kinds of
microprocessors. Key functions of this interface include the following:
Figure 19 shows the timing diagram for Motorola microprocessors with separate address and data buses. Members
of this microprocessor family include 2 MHz versions of the MC6800, MC6802 and MC6809. For the MC6809, the
chip select (CS) input signal is formed by NANDing the (E+Q) clocks and address decode output. For the MC6800
and MC6802, CS is formed by NANDing VMA and address decode output. On the falling edge of CS, the internal
logic senses the state of data strobe (DS). When DS is low, Motorola processor operation is selected.
Figure 20 shows the timing diagram for the Motorola MC68HC11 (1 MHz) microcontroller. The chip select (CS)
input is formed by NANDing address strobe (AS) and address decode output. Again, the MT8889C examines the
state of DS on the falling edge of CS to determine if the micro has a Motorola bus (when DS is low). Additionally, the
Texas Instruments TMS370CX5X is qualified to have a Motorola interface. Figure 14(a) summarizes connection of
these Motorola processors to the MT8889C DTMF transceiver.
Figures 21 and 22 are the timing diagrams for the Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro-controllers
with multiplexed address and data buses. The MT8889C latches in the state of RD on the falling edge of CS. When
RD is high, Intel processor operation is selected. By NANDing the address latch enable (ALE) output with the high-
byte address (P2) decode output, CS can be generated. Figure 14(b) summarizes the connection of these Intel
processors to the MT8889C transceiver.
NOTE: The adaptive micro interface relies on high-to-low transition on CS to recognize the microcontroller interface
and this pin must not be tied permanently low.
The adaptive micro interface provides access to five internal registers. The read-only Receive Data Register
contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data
Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is
accomplished with two control registers (see Tables 6 and 7), CRA and CRB, which have the same address. A write
operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the
same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-
only status register indicates the current transceiver state (see Table 8).
Continuous activity on DS/RD is not necessary to update the internal status registers.
senses whether input timing is that of an Intel or Motorola controller by monitoring the DS (RD), R/W (WR)
and CS inputs.
generates equivalent CS signal for internal operation for all processors.
differentiates between multiplexed and non-multiplexed microprocessor buses. Address and data are
latched in accordingly.
compatible with Motorola and Intel processors.
Microprocessor Interface
OSC1 OSC2
3.579545 MHz
MT8889C
Figure 13 - Common Crystal Connection
Zarlink Semiconductor Inc.
MT8889C
OSC1 OSC2
MT8889C
12
OSC1 OSC2
MT8889C
Data Sheet

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