MT8889CN Zarlink Semiconductor, Inc., MT8889CN Datasheet - Page 2

• Manufacturer Part Number: MT8889CN
• Description: Integrated DTMF Transceiver with Adaptive Micro Interface
• Manufacturer: Zarlink Semiconductor, Inc.

employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so
that frequencies within the specified passband can be detected. The adaptive micro interface allows
microcontrollers, such as the 68HC11, 80C51 and TMS370C50, to access the MT8889C internal registers.
Pin Description
R/W/WR
20
10
12
11
1
2
3
4
5
6
7
8
9
OSC1
OSC2
TONE
VRef
VSS
IN+
GS
CS
IN-
20 PIN PLASTIC DIP/SOIC
Pin #
24
10
11
12
13
14
1
2
3
4
5
6
7
10
1
2
3
4
5
6
7
8
9
28
12
13
14
15
17
1
2
4
6
7
8
9
20
19
18
17
16
15
14
13
12
11
R/W (WR) (Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible.
DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this
TONE
Name
OSC1
OSC2
V
RS0
V
IN+
GS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
IN-
CS
Ref
SS
Non-inverting op-amp input.
Inverting op-amp input.
Gain Select. Gives access to output of front end differential amplifier for
connection of feedback resistor.
Reference Voltage output (V
Ground (0V).
DTMF clock/oscillator input. Connect a 4.7M resistor to VSS if crystal oscillator
is used.
Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
Output from internal DTMF transmitter.
Chip Select input. This signal must be qualified externally by either address
strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal,
see Figure 14.
Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
input is only required when the device is being accessed. TTL compatible.
R/W/WR
OSC1
OSC2
TONE
VRef
VSS
IN+
GS
NC
NC
CS
IN-
Figure 2 - Pin Connections
Zarlink Semiconductor Inc.
10
11
12
1
2
3
4
5
6
7
8
9
24 PIN SSOP
MT8889C
2
24
23
22
21
20
19
18
17
16
15
14
13
DD
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
/2).
Description
OSC1
OSC2
VRef
VSS
NC
NC
NC
5
6
7
8
9
10
11
28 PIN PLCC
Data Sheet
25
24
23
22
21
20
19
NC
NC
NC
D3
D2
D1
D0