MT8889CSR Zarlink Semiconductor, Inc., MT8889CSR Datasheet - Page 16

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MT8889CSR

Manufacturer Part Number
MT8889CSR
Description
Integrated DTMF Transceiver with Adaptive Micro Interface
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT8889CSR1
Manufacturer:
ZARLINK
Quantity:
150
Company:
Part Number:
MT8889CSR1
Quantity:
240
MT8889C
AC Electrical Characteristics
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
16
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
DS/RD/WR clock frequency
DS/RD/WR cycle period
DS/RD/WR low pulse width
DS/RD/WR high pulse width
DS/RD/WR rise and fall time
R/W setup time
R/W hold time
Address setup time (RS0)
Address hold time (RS0)
Data hold time (read)
DS/RD to valid data delay (read)
Data setup time (write)
Data hold time (write)
Chip select setup time
Chip select hold time
Input Capacitance (data bus)
Output Capacitance (IRQ/CP)
2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration=40 ms. Tone pause=40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the composite signal have an equal amplitude.
6) The tone pair is deviated by
7) Bandwidth limited (3 kHz) Gaussian noise.
8) The precise dial tone frequencies are 350 and 440 Hz (
9) Guaranteed by design and characterization. Not subject to production testing.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) For guard time calculation purposes.
DS/RD/WR
Characteristics
°
C, V
DD
=5V, and for design aid only: not guaranteed and not subject to production testing
±
1.5 %
- MPU Interface
Figure 16 - DS/RD/WR Clock Pulse
±
2 Hz.
t
R
C
t
t
t
t
Sym
t
t
f
t
t
t
t
DHW
RWS
RWH
DSW
C
CYC
CYC
t
t
DHR
DDR
CSH
R,
t
CSS
CH
OUT
t
AS
AH
CL
IN
t
F
t
CH
±
Min
150
- Voltages are with respect to ground (V
2 %).
23
20
40
22
45
10
45
40
0
t
CYC
Typ
250
100
t
4.0
20
35
F
5
5
Max
100
20
t
CL
Units
MHz
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SS
Figure 16
Figure 16
Figure 16
Figure 16
Figure 16
Figures 17 & 18
Figures 17 & 18
Figures 17 - 20
Figures 17 - 20
Figures 17 - 20
Figures 17 - 20
Figures 17 - 20
Figures 17 - 20
Figures 17 - 20
Figures 17 - 20
), unless otherwise stated.
Conditions

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