MT8889CSR Zarlink Semiconductor, Inc., MT8889CSR Datasheet - Page 8

• Manufacturer Part Number: MT8889CSR
• Description: Integrated DTMF Transceiver with Adaptive Micro Interface
• Manufacturer: Zarlink Semiconductor, Inc.

MT8889C
The
correspond to V
waveform. The total harmonic distortion for a dual
tone can be calculated using Equation 2. V
correspond to the low group amplitude and high
group amplitude, respectively and V
of all the intermodulation components. The internal
switched-capacitor filter following the D/A converter
keeps distortion products down to a very low level as
shown in Figure 10.
DTMF Clock Circuit
The internal clock circuit is completed with the
addition of a standard television colour burst crystal.
The crystal specification is as follows:
Frequency:
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Maximum Series Resistance:150 ohms
Maximum Drive Level:
e.g.
A number of MT8889C devices can be connected as
shown in Figure 11 such that only one crystal is
required. Alternatively, the OSC1 inputs on all
devices can be driven from a TTL buffer with the
OSC2 outputs left unconnected.
Microprocessor Interface
The MT8889C design incorporates an adaptive
interface, which allows it to be connected to various
8
THD (%) = 100
OSC1 OSC2
3.579545 MHz
MT8889C
Fourier
CTS Knights MP036S
Toyocom TQC-203-A-9S
Figure 11 - Common Crystal Connection
Equation 2. THD (%) For a Dual Tone
components
2f
.... V
OSC1 OSC2
V
MT8889C
2
nf
2L
V
as measured on the output
+ V
2
3H
2
3.579545 MHz
±0.1%
Parallel
18pF
V
+ .. V
3L
2
2mW
L
of
+ .... V
+ V
2
nH
2
the
H
+ V
2
nL
2
IMD
2
+ V
OSC1 OSC2
IMD
tone
MT8889C
2
2H
is the sum
L
+
and V
output
H
kinds of microprocessors. Key functions of this
interface include the following:
•
•
•
•
•
Figure 17 shows the timing diagram for Motorola
microprocessors with separate address and data
buses. Members of this microprocessor family
include 2 MHz versions of the MC6800, MC6802 and
MC6809. For the MC6809, the chip select (CS) input
signal is formed by NANDing the (E+Q) clocks and
address decode output. For the MC6800 and
MC6802, CS is formed by NANDing VMA and
address decode output. On the falling edge of CS,
the internal logic senses the state of data strobe
(DS). When DS is low, Motorola processor operation
is selected.
Figure 18 shows the timing diagram for the Motorola
MC68HC11 (1 MHz) microcontroller. The chip select
(CS) input is formed by NANDing address strobe
(AS) and address decode output. Again, the
MT8889C examines the state of DS on the falling
edge of CS to determine if the micro has a Motorola
bus (when DS is low). Additionally, the Texas
Instruments TMS370CX5X is qualified to have a
Motorola
connection of these Motorola processors to the
MT8889C DTMF transceiver.
Figures 19 and 20 are the timing diagrams for the
Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro-
controllers with multiplexed address and data buses.
The MT8889C latches in the state of RD on the
falling edge of CS. When RD is high, Intel processor
operation is selected.
latch enable (ALE) output with the high-byte address
(P2) decode output, CS can be generated.
12(b) summarizes the connection of these Intel
processors to the MT8889C transceiver.
NOTE: The adaptive micro interface relies on high-
to-low
microcontroller interface and this pin must not be tied
permanently low.
Continuous activity on DS/RD is not necessary
to update the internal status registers.
senses whether input timing is that of an Intel or
Motorola controller by monitoring the DS (RD),
R/W (WR) and CS inputs.
generates equivalent CS signal for internal
operation for all processors.
differentiates between multiplexed and non-
multiplexed microprocessor buses. Address and
data are latched in accordingly.
compatible with Motorola and Intel processors.
transition
interface.
on
Figure
By NANDing the address
CS
to
12(a)
recognize
summarizes
Figure
the