MT8930CPR Zarlink Semiconductor, Inc., MT8930CPR Datasheet
MT8930CPR
Related parts for MT8930CPR
MT8930CPR Summary of contents
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Features • ETS 300-012, CCITT I.430 and ANSI T1.605 S/T interface • Full-duplex 2B+D, 192 kbit/s transmission • Link activation/deactivation • D-channel access contention resolution • Point-to-point, point-to-multipoint and star configurations • Master (NT)/Slave (TE) modes of operation • Exceeds ...
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MT8930C 1 28 HALF 2 27 C4b 26 F0b 3 25 F0od DSTi 23 DSTo 6 22 Cmode 7 21 CK/ R/W/WR, AFT/PRI 9 DS/RD, DinB 19 10 AS/ALE, P/ CS, DReq 17 ...
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Pin Description (continued) Pin # Name DIP PLCC 9 16 R/W WR Read/Write or Write Input (Cmode = 1): defines the data bus transfer as a read ( write (R/W=0) in Motorola bus mode. Redefined to ...
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MT8930C Pin Description (continued) Pin # Name DIP PLCC 17 26 SYNC/BA Synchronization/Bus Activity Output (Cmode = 0): output indicating synchronization to incoming RX frames when activation request is asserted and the deactivation request is ’0’ ( and ...
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Functional Description The MT8930C Subscriber Network Interface Circuit (SNIC multifunction transceiver providing a complete interface to the S/T Reference Point as specified in ETS 300-012, CCITT Recommendation I.430 and ANSI T1.605. Implementing point-to-point and point-to-multipoint transmission, the SNIC ...
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MT8930C Figure 4 - ST-BUS Channel Assignment 9-38 Intel microprocessor bus signals and timing. The SNIC also has provisions for a controllerless mode (Cmode=0), where the microprocessor port is redefined to allow access to the control/status registers via external hardware. ...
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MT8930C 9-39 ...
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MT8930C Line Code The line code used on the S-interface is a Pseudo ternary code with 100% pulse width as seen in Figure 6 below. Binary zeros are represented as marks on the line and successive marks will alternate in ...
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These contradicting standards place a restriction on all information input and output through the serial and parallel ports. Information transferred ...
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MT8930C Signals from Info0 No Signal Info2 Valid frame structure with all B, D, D-echo and A bits set to ‘0’ Info4 Valid frame with data D-echo channels. Bit A is set to 1. ...
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operating in adaptive timing TR is the line termination resistor = 100 Ω operating in fixed timing TR is the line termination resistor = 100 Ω Fiure 9 - Short ...
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MT8930C Channel Channel 0 1 Bit 7 F0b C4b ST-BUS Channel 31 BIT CELLS Bit 0 Figure 12 - Clock & Frame Alignment for ST-BUS Streams ST-BUS Interface The ST-BUS is a synchronous time division multiplexed serial bussing scheme with ...
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ST-BUS Clock ST-BUS Stream Channel MT8930C NT System F0b Frame Pulse F0od to TE System to TE Frame Pulse Input ST-BUS Stream eight SNICs in NT mode with physically independent S-Busses can be ...
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MT8930C Address Lines ...
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Diagnostic Register cleared. Once full activation is achieved the Diagnostic Register can be written to in order to enable the various test functions. HDLC Transceiver The HDLC Transceiver handles the bit oriented protocol structure and formats the D-channel as per ...
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MT8930C Interframe Time Fill When the HDLC Tranceiver is not sending packets, the transmitter can be in one of two states mentioned below depending on the status of the IFTF bit in the HDLC Control Register 1. i) Idle State ...
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HIGH, before writing the next byte into the FIFO. This bit is cleared automatically once the byte is written to the Transmit FIFO. When the ‘flagged’ byte reaches the bottom of the FIFO, a frame abort sequence is sent ...
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MT8930C distinguished by the fact that it has no “Last Byte” status on any of its bytes. iv) Idle Channel While receiving the idle channel, the idle bit in the HDLC status register remains set. v) Transparent Data Transfer By ...
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BIT NAME (3) B7 CH3i If ’1’, then the ST-BUS channel 3 input port is enabled (B2-channel). If ’0’, then the channel is disabled, and will read FF (3) B6 CH2i If ’1’, then the ST-BUS channel 2 input port ...
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MT8930C BIT NAME B7-B5 NA Keep at ’0’ for normal operation. B4 Trans A ’1’ will place the HDLC in a transparent mode. This will perform the serial to parallel or parallel to serial conversion without inserting or deleting the ...
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BIT NAME B7 EnDcoll A ’1’ will enable the D-channel collision interrupt. A ’0’ will disable it. This bit is available only in TE mode. B6 EnEOPD A ’1’ will enable the received End of Packet interrupt. A ’0’ will ...
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MT8930C BIT NAME B7-B2 R1A7-R1A2 A six bit mask used to interrogate the first byte of the received address (where B7 is MSB). If address recognition is enabled, any packet failing the address comparison will not be stored in the ...
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BIT NAME B7-B6 Loop The status of these two bits determine which type of loopback performed: B5 FSync If ’1’, the device will maintain frame synchronization even after losing the framing sequence (i.e., if the device is ...
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MT8930C BIT NAME B7 AR Setting this bit will initiate the activation of the S-Bus. If ’0’, the device will remain in the present state Setting this bit will initiate the deactivation of the S-Bus. If ’0’, the ...
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BIT NAME B7 Sync/BA This bit is set if the device has achieved frame synchronization while the activation request is asserted ( and AR = 1). If there is a deactivation request or that AR is low ( ...
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MT8930C Applications The MT8930C is useful in a wide variety of ISDN applications. Being used at both the Network Termination (NT) and Terminal Equipment (TE) ends of the line, the SNIC finds application on digital subscriber line cards and in ...
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Termination Network MH89101 U Reference Point Figure 17 - NT1 using the MT8910-1 (DSLIC) and MT8930C (SNIC) MT8930C ‡ R LTx V Bias ‡ R LRx 1:2 2kΩ Data Port IRQ + ...
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MT8930C MT8930C AD0-AD7 Connections to interface to MC6809 Figure 19 - Interfacing to the MC6802 Microprocessor ETS 300-012 NT&TE Line Interface Figures 20, 21 and 22 show the recommended line interface circuits for meeting the ETS 300-012 requirements. These circuits ...
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In Figure 21, two types of diodes (germanium 1N270 or schottky MBD301) can be used for D5,6. 1N270 will leave more margin for pulse template and longitudinal conversion loss. However, MBD301 will leave more margin for impedance template. All other ...
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MT8930C MT8930C D5 LTx Bias R1 LRx Figure 21 - ETS 300-012 NT & TE Line Interface for VAC X027 or X028 ...
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MT8930C R1 LTx Bias R2 LRx V SS Figure 23 - Proprietary NT & TE Line Interface ...
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MT8930C Absolute Maximum Ratings Parameters 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions ...
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AC Electrical Characteristics Characteristics 1 F0b input pulse width 2 Frame pulse (F0b) set-up time 3 Frame pulse (F0b) hold time 4 C4b input clock period 5 C4b pulse width High or Low 6 C4b transition time 7 F0od delay ...
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MT8930C AC Electrical Characteristics Characteristics 1 F0b output pulse width 2 C4b to (F0b) delay 3 C4b to (F0b) hold time 4 C4b output clock period 5 C4b pulse width High or Low 6 C4b transition time 7 F0od delay ...
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AC Electrical Characteristics Characteristics 1 Chip select setup time 2 Chip select hold time 3 Address Latch pulse width 4 Address setup time 5 Address hold time 6 Data setup time - Write 7 Data hold time - Write 8 ...
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MT8930C AC Electrical Characteristics Characteristics 1 Chip select setup time 2 Chip select hold time 3 Address strobe pulse width 4 Data strobe setup time 5 Data strobe hold 6 Data strobe pulse width 7 Read/Write setup time 8 Read/Write ...
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AC Electrical Characteristics Characteristics 1 C inputs setup time (TE Mode) mode 2 C inputs setup time (NT Mode) mode 3 C inputs hold time (TE Mode) mode 4 C inputs hold time (NT Mode) mode 5 C outputs delay ...
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MT8930C Notes: 9-70 ...
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Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...
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Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...
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Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...
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