CS4382A

Manufacturer Part NumberCS4382A
Description192 kHz 8-Channel D/A Converter
ManufacturerCirrus Logic
CS4382A datasheet
 


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114 dB, 192 kHz 8-channel D/A Converter
Features
Advanced Multi-bit Delta Sigma Architecture
24-bit Conversion
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
Direct Stream Digital Mode
– On-chip 50 kHz filter
– Matched PCM and DSD analog output
levels
Selectable Digital Filters
Volume Control with 1-dB Step Size and Soft
Ramp
Low Clock Jitter Sensitivity
+5 V Analog Supply, +2.5 V Digital Supply
Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
Control & Serial Audio Port
Supplies = 1.8 V to 5 V
Hardware Mode or
2
I
C/SPI Software Mode
Control Data
Reset
PCM Serial
Audio Input
DSD Audio
http://www.cirrus.com
Description
The CS4382A is a complete 8-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
one-dB step size volume control, ATAPI channel mix-
ing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma mod-
ulator which includes mismatch shaping technology that
eliminates distortion due to capacitor mismatch. Follow-
ing this stage is a multi-element switched capacitor
stage and low-pass filter with differential analog
outputs.
The CS4382A also has a proprietary DSD processor
which allows for 50 kHz on-chip filtering without an in-
termediate decimation stage.
The CS4382A accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excel-
lent sound quality. These features are ideal for multi-
channel audio systems including SACD players, A/V re-
ceivers,
processors, sound cards and automotive audio
systems.
ORDERING INFORMATION
See page 41.
Digital Supply = 2.5 V
Register/Hardware
Configuration
Multi-bit ∆Σ
Volume
Digital
Controls
Filters
8
Modulators
DSD Processor
-50 kHz filter
Input
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
CS4382A
digital
TV’s,
mixing
consoles,
Analog Supply = 5 V
Internal Voltage
Reference
Switch-Cap
8
Differential
DAC and
Outputs
Analog Filters
8
External Mute
Mute Signals
Control
2
effects
APR '05
DS618PP1

CS4382A Summary of contents

  • Page 1

    ... The CS4382A also has a proprietary DSD processor which allows for 50 kHz on-chip filtering without an in- termediate decimation stage. The CS4382A accepts PCM data at sample rates from 4 kHz to 216 kHz, DSD audio data, and delivers excel- lent sound quality. These features are ideal for multi- ...

  • Page 2

    ... Interpolation Filter Select (FILT_SEL).................................................................. 36 5.4.2 De-Emphasis Control (DEM) ............................................................................... 36 5.4.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) ................................... 36 5.5 Invert Control (address 05h) ............................................................................................ 37 5.5.1 Invert Signal Polarity (Inv_Xx).............................................................................. 37 5.6 Mixing Control Pair 1 (Channels A1 & B1)(address 06h) Mixing Control Pair 2 (Channels A2 & B2)(address 09h Write ............................................................................................ Read ............................................................................................ 29 ............................................................................... 30 CS4382A DS618PP1 ...

  • Page 3

    ... Functional Mode (FM).......................................................................................... 38 5.7 Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh) .......................................... 39 5.7.1 Mute (MUTE) ....................................................................................................... 39 5.7.2 Volume Control (xx_VOL) .................................................................................... 39 5.8 Chip Revision (address 12h) ........................................................................................... 40 5.8.1 Part Number ID (part) [Read Only] ...................................................................... 40 6. PARAMETER DEFINITIONS.................................................................................................... 41 7. REFERENCES.......................................................................................................................... 41 8. ORDERING INFORMATION .................................................................................................... 41 9. PACKAGE DIMENSIONS ........................................................................................................ 42 10. APPENDIX ............................................................................................................................. 43 DS618PP1 CS4382A 3 ...

  • Page 4

    ... Figure 36. Quad-Speed (fast) Transition Band ......................................................................................... 45 Figure 37. Quad-Speed (fast) Transition Band (detail) ............................................................................. 46 Figure 38. Quad-Speed (fast) Passband Ripple ....................................................................................... 46 Figure 39. Quad-Speed (slow) Stopband Rejection.................................................................................. 46 Figure 40. Quad-Speed (slow) Transition Band........................................................................................ 46 Figure 41. Quad-Speed (slow) Transition Band (detail)............................................................................ 46 Figure 42. Quad-Speed (slow) Passband Ripple...................................................................................... Format ............................................................................................... Mode................................................................................................. 29 CS4382A DS618PP1 ...

  • Page 5

    ... Table 2. Digital Interface Format, Stand-Alone Mode Options...................................................... 21 Table 3. Mode Selection, Stand-Alone Mode Options .................................................................. 21 Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................... 21 Table 5. Digital Interface Formats - PCM Mode............................................................................ 33 Table 6. Digital Interface Formats - DSD Mode ............................................................................ 33 Table 7. ATAPI Decode ................................................................................................................ 38 Table 8. Example Digital Volume Settings .................................................................................... 39 Table 9. Revision History ............................................................................................................. 47 DS618PP1 CS4382A 5 ...

  • Page 6

    ... DSDB1 2 35 DSDA1 GND 5 32 MCLK 6 CS4382A SDIN1 8 29 SCLK 9 28 TST 10 27 SDIN2 11 26 TST Pin Description CS4382A AOUTA2- AOUTA2+ AOUTB2+ AOUTB2- VA GND AOUTA3- AOUTA3+ AOUTB3+ AOUTB3- AOUTA4- AOUTA4+ DS618PP1 ...

  • Page 7

    ... Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. DSDB1 2 DSDA2 1 DSDB2 48 DSDA3 47 DSDB3 46 DSDA4 45 DSDB4 44 DS618PP1 Pin Description Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in CS4382A 2 C mode as shown in the Typical 2 C mode and requires an 7 ...

  • Page 8

    ... VLS Control port interface power VLC -CQZ T -EQZ Symbol Analog power VA Digital internal power VD VLS VLC Any Pin Except Supplies I in Serial data port interface V IND-S Control port interface V IND stg CS4382A Min Typ Max 4.75 5.0 5.25 2.37 2.5 2.63 1.71 5.0 5.25 1.71 5.0 5.25 -10 - +70 A -40 - +105 Min Max -0.3 6 ...

  • Page 9

    ... DAC ANALOG CHARACTERISTICS Full-Scale Output Sine Wave, 997 Hz ment Bandwidth kHz, unless otherwise specified. Parameters CS4382A-CQZ Dynamic Performance - All PCM modes and DSD Specified Temperature Range Dynamic Range (Note 2) unweighted Total Harmonic Distortion + Noise (Note 2) 16-bit Idle Channel Noise / Signal-to-noise ratio ...

  • Page 10

    ... I A VD= 2 VLS 2.5 V normal operation (Note 6) power-down θ JA θ kHz) PSRR (60 Hz) and includes attenuation due CS4382A Min Typ Max - 110 - - 0 100 - 134%•V 136%• 96%•V 98%• 130 ...

  • Page 11

    ... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .583 (Note 10 -0.01 dB corner corner kHz -0.01 .635 (Note 10 CS4382A Typ Max Unit - .454 Fs - .499 Fs - +0. 10.4/ ±0. ±0. ±0.09 ...

  • Page 12

    ... kHz - to -0.01 dB corner corner kHz -0.01 .792 (Note 10 -0.01 dB corner corner kHz -0.01 .868 (Note 10 Min corner kHz -0.05 27 CS4382A Typ Max Unit - 0.417 Fs - 0.499 Fs - +0. 7.8/ ±0. ±0. ±0.14 ...

  • Page 13

    ... Any pin except supplies. Transient currents ±100 mA on the input pins will not cause SCR latch- up DS618PP1 Symbol Min (Note 13 Serial I/O V 70% IH Control I/O V 70% IH Serial I Control I Control I/O V 80% OH Control I max CS4382A Typ Max Units µA - ± ...

  • Page 14

    ... See Table 1 on page 20 for suggested MCLK frequencies. LRCK SCLK SDINx pF) L (Note 14) (Note 15) Single-Speed Mode Double-Speed Mode Quad-Speed Mode t t lcks sckh MSB Figure 1. Serial Audio Interface Timing CS4382A Symbol Min Max 1 - 1.024 55 108 s F 100 216 s ...

  • Page 15

    ... DSD_SCLK rising to DSD_A or DSD_B hold time DSD_SCLK DSDxx Figure 2. Direct Stream Digital - Serial Audio Input Timing DS618PP1 = 20 pF) L Symbol t sclkl t sclkh (64x Oversampled) (128x Oversampled) t sdlrs t sdh t sclkl t t sdlrs sdh CS4382A Min Typ Max Unit 160 - - ns 160 - - ns 1.024 - 3.2 MHz 2.048 - 6.4 ...

  • Page 16

    ... Repeated Start t high t t sud t sust hdd 2 Figure 3. Control Port Timing - I C Format CS4382A 2 C FORMAT Min Max Unit - 100 kHz 500 - ns 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ µs 250 - ns ...

  • Page 17

    ... L Symbol f sclk t srs t spi t csh t css t scl t sch t dsu css t scl t sch dsu t dh Figure 4. Control Port Timing - SPI Format CS4382A FORMAT ™ Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ ...

  • Page 18

    ... MUTEC1 44 DSDB4 MUTEC234 42 DSD_SCLK 19 RST 15 SCL/CCLK 16 SDA/CDIN 17 ADO/CS Note* FILT+ 18 VLC 0.1 µF GND GND TST CS4382A + 0.1 µF 1 µF 39 Analog Conditioning 40 and Muting 38 Analog Conditioning 37 and Muting 35 Analog Conditioning 36 and Muting 34 Analog Conditioning 33 and Muting 29 Analog Conditioning 30 and Muting 28 ...

  • Page 19

    ... DSDB4 DSD AOUTB4- Note Optional 47 KΩ 42 MUTEC234 M3(DSD_SCLK Mode RST 18 VLC 0.1 µF GND GND 5 31 CS4382A + 0.1 µF 1 µF 39 Analog Conditioning 40 and Muting 38 Analog Conditioning 37 and Muting Mute 41 Drive 35 Analog Conditioning 36 and Muting 34 Analog Conditioning 33 and Muting 29 ...

  • Page 20

    ... The Left/Right Clock (LRCK) determines which channel is currently being input on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4382A can be configured in hardware mode by the M0, M1 and DSD_EN pins and in software 2 mode through SPI ...

  • Page 21

    ... DSD data with a 2x MCLK to DSD data rate 0 128x oversampled DSD data with a 3x MCLK to DSD data rate 1 128x oversampled DSD data with a 4x MCLK to DSD data rate 0 128x oversampled DSD data with a 6x MCLK to DSD data rate 1 CS4382A FORMAT FIGURE ...

  • Page 22

    ... LSB MSB 2 Figure 8. Format 24-bit Data Figure 9. Format 2 - Right-Justified 16-bit Data Figure 10. Format 3 - Right-Justified 24-bit Data CS4382A Right Channel + LSB Right Channel + LSB Right Channel ...

  • Page 23

    ... Oversampling Modes The CS4382A operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the DSD_EN, M3 and M2 pins in hardware mode or the FM bits in software mode. Single- Speed mode supports input sample rates kHz and uses a 128x oversampling ratio. Double-Speed mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x ...

  • Page 24

    ... Right Chan nel Audio D ata Figure 14. ATAPI Block Diagram (x = channel pair Gain dB T1=50 µs 0dB F1 F2 3.183 kHz 10.61 kHz Figure 13. De-Emphasis Curve A Channel Volume Control Σ B Channel Volume Control CS4382A µs Frequency MUTE Aout Ax Σ MUTE AoutBx DS618PP1 ...

  • Page 25

    ... The Typical Connection Diagram shows the recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4382A should be con- nected to the analog ground plane. ...

  • Page 26

    ... Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. Please see the CDB4382A data sheet for a suggested mute circuit. 26 Figure 15. Full-Scale Output Figure 16. Recommended Output Filter CS4382A 3.85 V 2.5 V 1.15 V 3. ...

  • Page 27

    ... DAC functions (such as changing sample rates or clock sources). The mute bits may then be released after clocks have settled and the proper modes have been set required to have the device held in reset if the minimum high/low time specs of MCLK can not be met during clock source changes. DS618PP1 CS4382A 27 ...

  • Page 28

    ... START condition and follow the procedure detailed from step further writes to other registers are desired, initiate a STOP condition to the bus SPI bus followed by the address byte. The upper 6 bits must writes to other registers are desired necessary to ini- CS4382A 2 C writes or reads and SPI DS618PP1 ...

  • Page 29

    ... C read is the first operation performed on the device reads from other registers are desired necessary Read section further reads from other registers are N ote 1 ADDR DATA R/W ACK ACK AD 0 1-8 2 Figure 17. Control Port Timing Mode CS4382A DATA ACK 1-8 Stop ...

  • Page 30

    ... Default = ‘0’ Disabled 1 - Enabled 3.15.2 MAP4-0 (MEMORY ADDRESS POINTER) Default = ‘00000’ 30 CHIP MAP ADDRESS 0011000 MSB R/W byte ory Address Pointer Figure 18. Control Port Timing, SPI mode MAP4 MAP3 CS4382A DATA LSB byte MAP2 MAP1 MAP0 0 0 DS618PP1 0 0 ...

  • Page 31

    ... B3_VOL6 B3_VOL5 B3_VOL4 P4ATAPI4 P4ATAPI4 P4ATAPI2 P4ATAPI1 A4_VOL6 A4_VOL5 A4_VOL4 B4_VOL6 B4_VOL5 B4_VOL4 PART3 PART2 PART1 CS4382A Reserved Reserved Reserved AMUTE Reserved Reserved DEM1 DEM0 INV_B2 INV_A2 INV_B1 P1ATAPI0 ...

  • Page 32

    ... When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state advised that changes to these bits be made while the power down bit is enabled to eliminate the possibility of audible artifacts mode and write only in SPI, unless otherwise noted DAC4_DIS DAC3_DIS CS4382A DAC2_DIS DAC1_DIS PDN DS618PP1 ...

  • Page 33

    ... DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate CS4382A ...

  • Page 34

    ... The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Con- trol Byte, and the other Volume Control Bytes are ignored when this function is enabled RMP_UP MUTEC+/- CS4382A AMUTE Reserved MUTEC DS618PP1 ...

  • Page 35

    ... DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more information on the use of the mute control function see the MUTEC1 and MUTEC234 pins in section 8. DS618PP1 CS4382A 35 ...

  • Page 36

    ... Loss of clocks or a change in the FM bits will always cause an immediate mute; Unmute in these conditions is affected by the RMP_UP bit. Notes: For best results recommended that this feature be used in conjunction with the RMP_UP bit FILT_SEL Reserved CS4382A DEM1 DEM0 RMP_DN DS618PP1 ...

  • Page 37

    ... ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 7 and Figure 14 for additional information. DS618PP1 INV_A3 INV_B2 PxATAPI2 PxATAPI1 CS4382A INV_A2 INV_B1 INV_A1 PxATAPI0 PxFM1 PxFM0 ...

  • Page 38

    ... MUTE 1 0 MUTE 1 1 MUTE [(aL+bR)/ [(aL+bR)/ [(bL+aR)/ [(aL+bR)/2] Table 7. ATAPI Decode CS4382A AOUTBx MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] aL MUTE b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(bL+aR)/2] aL MUTE [(aL+bR)/2] MUTE bR ...

  • Page 39

    ... DS618PP1 xx_VOL4 xx_VOL3 Decimal Value Table 8. Example Digital Volume Settings CS4382A 2 1 xx_VOL2 xx_VOL1 xx_VOL0 0 0 Volume Setting 0 dB -20 dB -40 dB - ...

  • Page 40

    ... Chip Revision (address 12h PART4 PART3 PART2 0 1 5.8.1 Part Number ID (part) [Read Only] CS4382A 01110 - 000 - Revision A Function: This read-only register can be used to identify the model and revision number of the device PART1 PART0 CS4382A Reserved Reserved Reserved DS618PP1 ...

  • Page 41

    ... CS4382A channel D/A Converter CDB4382A CS4382A Evaluation Board DS618PP1 Package Pb-Free Grade Commercial 48-pin YES LQFP Automotive -40° to +105° CS4382A Temp Range Container Order # Tray CS4382A-CQZ -10° to +70° C Tape & Reel CS4382A-CQZR Tray CS4382A-EQZ Tape & Reel CS4382A-EQZR - - CDB4382A 41 ...

  • Page 42

    ... Controlling dimension is mm. JEDEC Designation: MS022 ∝ L INCHES NOM MAX 0.055 0.063 0.004 0.006 0.009 0.011 0.354 0.366 0.28 0.280 0.354 0.366 0.28 0.280 0.020 0.024 0.24 0.030 4° 7.000° CS4382A A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7.10 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7.10 0.40 0.50 BSC 0.60 0.45 0.60 0.75 0.00° ...

  • Page 43

    ... Figure 20. Single-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 −0.005 −0.01 −0.015 −0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 22. Single-Speed (fast) Passband Ripple 0 −20 −40 −60 −80 −100 −120 0.8 0.9 1 0.4 0.42 Figure 24. Single-Speed (slow) Transition Band CS4382A 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.6 0.5 0.6 43 ...

  • Page 44

    ... Figure 29. Double-Speed (fast) Transition Band (detail) 44 0.02 0.015 0.01 0.005 0 −0.005 −0.01 −0.015 −0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 26. Single-Speed (slow) Passband Ripple 100 120 0.4 0.42 0.8 0.9 1 Figure 28. Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 30. Double-Speed (fast) Passband Ripple CS4382A 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) DS618PP1 0.5 0.6 0.5 ...

  • Page 45

    ... Frequency(normalized to Fs) Figure 35. Quad-Speed (fast) Stopband Rejection DS618PP1 100 120 0.2 0.7 0.8 0.9 1 Figure 32. Double-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 Figure 34. Double-Speed (slow) Passband Ripple 100 120 0.7 0.8 0.9 1 0.2 Figure 36. Quad-Speed (fast) Transition Band CS4382A 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.35 0.8 45 ...

  • Page 46

    ... Frequency(normalized to Fs) Figure 41. Quad-Speed (slow) Transition Band (detail) 46 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 0 0.52 0.53 0.54 0.55 Figure 38. Quad-Speed (fast) Passband Ripple 100 120 0.1 0.2 0.7 0.8 0.9 1 Figure 40. Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.02 Figure 42. Quad-Speed (slow) Passband Ripple CS4382A 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.04 0.06 0.08 0.1 Frequency(normalized to Fs) DS618PP1 0.9 0.12 ...

  • Page 47

    ... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. DS618PP1 Table 9. Revision History Changes Initial Release Updated output impedance spec on page 10 Improved interchannel isolation spec on page 10 Updated Legal text Re-formatted ordering information CS4382A 47 ...