CS4382A Cirrus Logic, CS4382A Datasheet - Page 27

• Manufacturer Part Number: CS4382A
• Description: 192 kHz 8-Channel D/A Converter
• Manufacturer: Cirrus Logic

DS618PP1
3.12
3.12.1 Hardware Mode
3.12.2 Software Mode
3.13
Recommended Power-Up Sequence
Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK can not be met
during clock source changes.
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
2. Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in
3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.
clocks are locked to the appropriate frequencies, as discussed in section 3.1. In this state, the registers
are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.
If RST can not be held low long enough the SDINx pins should remain static low until all other clocks
are stable, and if possible the RST should be toggled low again once the system is stable.
Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024
LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
appropriate frequencies, as discussed in section 3.1. In this state, the registers are reset to the default
settings, FILT+ will remain low, and VQ will be connected to VA/2.
Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode).
completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the format
and mode control bits to the desired settings.
If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will
enter Hardware mode and begin to operate with the M0-M3 as the mode settings. CPEN bit may be
written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit can
not be set in time then the SDINx pins should remain static low (this way no audio data can be
converted incorrectly by the hardware mode settings).
CS4382A
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