CS4382A Cirrus Logic, CS4382A Datasheet - Page 28

• Manufacturer Part Number: CS4382A
• Description: 192 kHz 8-Channel D/A Converter
• Manufacturer: Cirrus Logic

28
3.14
3.14.1 MAP Auto Increment
3.14.2 I
Control Port Interface
The control port is used to load all the internal register settings in order to operate in software mode (see
the “Parameter Definitions” on page 41). The operation of the control port may be completely asynchronous
with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates in one of two modes: I
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the
MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I
writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes
of successive registers.
In the I
control port clock, SCL (see Figure 17 for the clock to data relationship). There is no CS pin. Pin AD0 en-
ables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND as required,
before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after
power-up, SPI mode will be selected.
3.14.2.1 I
2
C Mode
To write to the device, follow the procedure below while adhering to the control port Switching Specifi-
cations in section 2.
1. Initiate a START condition to the I
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to
by the MAP.
4. If the INCR bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I
tiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to
other registers are desired, initiate a STOP condition to the bus.
2
C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
2
C Write
2
C bus followed by the address byte. The upper 6 bits must be
2
C writes to other registers are desired, it is necessary to ini-
2
C or SPI.
2
C writes or reads and SPI
CS4382A
DS618PP1