CS4382A Cirrus Logic, CS4382A Datasheet - Page 33

• Manufacturer Part Number: CS4382A
• Description: 192 kHz 8-Channel D/A Converter
• Manufacturer: Cirrus Logic

DS618PP1
5.1.5 Power Down (PDN)
5.2
5.2.1 Digital Interface Format (dif)
Reserved
DIF2
DIF2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
7
Mode Control 2 (address 02h)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be dis-
abled before normal operation in Control Port mode can occur.
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine wheth-
er PCM or DSD mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 7-12.
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required Mas-
ter clock to DSD data rate is defined by the Digital Interface Format pins.
DIF1
0
0
1
1
0
0
1
1
DIF1
0
0
1
1
0
0
1
1
DIF2
6
0
DIF0
0
1
0
1
0
1
0
1
DIFO
Table 6. Digital Interface Formats - DSD Mode
Left Justified, up to 24-bit data
I
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Reserved
2
Table 5. Digital Interface Formats - PCM Mode
S, up to 24-bit data
0
1
0
1
0
1
0
1
DIF1
5
0
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
DESCRIPTION
DIF0
0
4
Reserved
DESCRIPTION
3
0
Reserved
2
0
Format
0
1
2
3
4
5
-
-
Reserved
0
1
FIGURE
10
11
12
7
8
9
CS4382A
Reserved
0
0
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