CY7C4841-10AC Cypress Semiconductor Corp, CY7C4841-10AC Datasheet
CY7C4841-10AC
Specifications of CY7C4841-10AC
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CY7C4841-10AC Summary of contents
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... Double 256 x 9 (CY7C4801) • Double 512 x 9 (CY7C4811) • Double (CY7C4821) • Double (CY7C4831) • Double (CY7C4841) • Double (CY7C4851) • Functionally equivalent to two CY7C4201/4211/4221/ 4231/4241/4251 FIFOs in a single package • 0.65 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10 ns read/write cycle times) • ...
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... THREE–STATE OUTPUT REGISTER 0-8 RCLKA OEB QB 0-8 TQFP Top View CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 WENA2/LDA 10 CY7C4851 WCLKA 11 WENA1 12 RSA CY7C4801/4811/4821 CY7C4831/4841/4851 LDA FLAG LDB EFA PAEA PAFA FLAG FFA EFB PAEB PAFB FFB READ READ POINTER B READ READ CONTROL B RCLKB ...
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... C to +150 C Operating Range +125 C Range 0.5V to +7.0V Commercial Industrial 0.5V to +7.0V 0.5V to +7.0V Notes the “instant on” case temperature. A CY7C4801/4811/4821 CY7C4831/4841/4851 7C48X1-25 7C48X1- CY7C4831 CY7C4841 Double Double Double 64-pin TQFP 64-pin TQFP Ambient Temperature + + CY7C4851 64-pin TQFP 10% 5V 10% Page ...
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Pin Definitions Signal Name Description I/O DA Data Inputs Data Inputs Data Outputs Data Outputs Write Enable 1 WENA1 WENB1 Write Enable 2 WENA2/LDA Load WENB2/LDB Dual ...
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Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage IX Current [3] I Output Short OS Circuit ...
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Switching Characteristics Over the Operating Range Parameter Description f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock HIGH Time CLKH t Clock LOW Time CLKL t Data Set-Up Time DS t Data ...
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Switching Waveforms Write Cycle Timing WCLKA (WCLKB ( WENA1 (WENB1) WENA2(WENB2) (if applicable) FFA (FFB) t SKEW1 RCLKA (RCLKB) RENA1,RENB2 (RENB1, RENB2) Read Cycle Timing RCLKA (RCLKB) t ENS RENA1,RENA2 (RENB1,RENB2) EFA(EFB) ...
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Switching Waveforms (continued) [12] Reset Timing RSA(RSB) RENA1, RENA2 (RENB1,RENB2) WENA1 (WENB1) WENA2/LDA [14] (WENB2/LDB) EFA, PAEA (EFB, PAEB) FFA, PAFA (FFB, PAFB ( Notes: 12. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be ...
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Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLKA,WCLKB (FIRSTVALID WRITE ( ENS WENA1(WENB1) WENA2(WENB2) (if applicable) RCLKA(RCLKB) EFA(EFB) RENA1, RENA2 ...
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Switching Waveforms (continued) Empty Flag Timing WCLKA,WCLKB t DS DATA WRITE1 ( ENH ENS WENA1(WENB1 ENS ENH WENA2(WENB2) (if applicable) t FRL RCLKA(RCLKB) t SKEW1 EFA(EFB) RENA1, RENA2 ...
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Switching Waveforms (continued) Full Flag Timing NO WRITE WCLKA,WCLKB [10] t SKEW1 ( FFA(FFB) WENA1(WENB1) WENA2(WENB2) (if applicable) RCLKA(RCLKB) t ENS RENA1, RENA2 (RENB1,RENB2) LOW OEA(OEB) DATA IN OUTPUT REGISTER QA QA ...
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... If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when (PAFA,PAFB) goes LOW. 21. (PAFA,PAFB) offset = m. 22. 256-m words in FIFO for CY7C4801, 512-m words for CY7C4811, 1024-m words for CY7C4821, 2048-m words for CY7C4831, 4096-m words for CY7C4841, 8192-m words for CY7C4851. ...
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Switching Waveforms (continued) Write Programmable Registers t CLK t CLKH WCLKA,WCLKB t ENS WENA2/LDA (WENB2/LDB) t ENS WENA1(WENB1 ( Read Programmable Registers t CLK t CLKH RCLKA(RCLKB) t ENS WENA2/LDA ...
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Architecture The CY7C48X1 functions as two independent FIFOs in a single package, each with its own separate set of controls. The device con- sists of two arrays of 256 to 8K words of 9 bits each (imple- mented by a ...
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... LOW-to-HIGH transition of (WCLKA,WCLKB) by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4801 (256–m), CY7C4811 (512–m), CY7C4821 (1K–m), CY7C4831 (2K–m), CY7C4841 (4K–m), and CY7C4851 (8K–m). (PAFA,PAFB) is set HIGH by the LOW-to-HIGH transition of (WCLKA,WCLKB) when the number of available memory locations is greater than m ...
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... CY7C4801 0 0 [25 (n+1) to (256-(m+1)) (n+1) to (512-(m+1)) [26] (256 m) to 255 (512 m) 256 512 Number of Words in FIFO CY7C4831 CY7C4841 0 0 [25] [25 (n+1) to (2048 (m+1)) (n+1) to (4096 (m+1)) (n+1) to (8192 (m+1)) [26] [26] (2048 m) to 2047 (4096 m) 2048 4096 Notes: 25. n =Empty Offset (n=7 default value). ...
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... LOW at Reset so that the pin operates as a control to load and read the programma- ble flag offsets. RESET (RSA,RSB CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 CY7C4851 (PAFA,PAFB) Read Enable 2 (RENA2,RENB2) Used in a Single Device Configuration. CY7C4801/4811/4821 CY7C4831/4841/4851 DATA OUT ...
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Width Expansion Configuration Word width may be increased simply by connecting the corre- sponding input control signals of FIFOs A and B. A composite flag should be created for each of the end-point status flags EFA and EFB, also FFA ...
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... RENA2 CC WENA2 RCLKA WCLKA OEA WENA1 9 RENA1 CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 CY7C4851 RAM ARRAY B RCLKB WENB1 RENB1 WCLKB OEB WENB2 RENB2 V CC data. a typical application would have the expansion logic al- ternate data access from one device to the next in a sequential manner ...
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Ordering Information Double 256x9 FIFO Speed (ns) Ordering Code 10 CY7C4801-10AC CY7C4801-10AI 15 CY7C4801-15AC CY7C4801-15AI 25 CY7C4801-25AC CY7C4801-25AI 35 CY7C4801-35AC CY7C4801-35AI Double 512x9 FIFO Speed (ns) Ordering Code 10 CY7C4811-10AC CY7C4811-10AI 15 CY7C4811-15AC CY7C4811-15AI 25 CY7C4811-25AC CY7C4811-25AI 35 CY7C4811-35AC CY7C4811-35AI ...
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... Ordering Information (continued) Double 2Kx9 FIFO Speed (ns) Ordering Code 10 CY7C4831-10AC CY7C4831-10AI 15 CY7C4831-15AC CY7C4831-15AI 25 CY7C4831-25AC CY7C4831-25AI 35 CY7C4831-35AC CY7C4831-35AI Double 4Kx9 FIFO Speed (ns) Ordering Code 10 CY7C4841-10AC CY7C4841-10AI 15 CY7C4841-15AC CY7C4841-15AI 25 CY7C4841-25AC CY7C4841-25AI 35 CY7C4841-35AC CY7C4841-35AI Double 8Kx9 FIFO Speed (ns) Ordering Code 10 CY7C4851-10AC CY7C4851-10AI 15 CY7C4851-15AC CY7C4851-15AI 25 CY7C4851-25AC ...
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... Document #: 38-06005 Rev. ** © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...
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Document Title: CY7C4801/4811/4821/CY7C4831.4841/4851 256/512/1K/2K/4K/ Double Sync (TM) Fifos Document Number: 38-06005 Issue REV. ECN NO. Date ** 106466 07/11/01 Document #: 38-06005 Rev. ** Orig. of Change Description of Change SZV Change from Spec Number: 38-00538 to 38-06005 ...