AD9639 Analog Devices, Inc., AD9639 Datasheet
AD9639
Related parts for AD9639
AD9639 Summary of contents
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... PLL distributes and multiplies up to produce the corresponding data rate clock. 3. The JESD204 coded data rate supports up to 4.2 Gbps per channel. 4. The AD9639 operates from a single 1.8 V power supply. 5. Flexible synchronization schemes and programmable mode pins are available on-chip temperature sensor is included. ...
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... AD9639 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagram ........................................................................... 7 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 Equivalent Circuits ......................................................................... 15 REVISION HISTORY 5/09— ...
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... Full 10 Full 1.7 1.8 1.9 Full 1.7 1.8 1.9 Full 535 570 Full 98 105 Full 1.139 1.215 Full 3 Full 152 Full −95 Full −90 Rev Page AD9639 AD9639BCPZ-210 Min Typ Max Unit 12 Bits Guaranteed −2 ± −2 0.9 2 ±0.28 ±0.6 LSB ±0.7 ±1.3 LSB 1.25 V p-p 1 ...
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... Min Typ Max Full 63.5 64.5 25°C 64.1 Full 63.3 64.4 25°C 63.9 Full 10.2 10.4 25°C 10.3 Full 87.5 78.6 25°C 82 Full 79 74 25°C 84 Full 96 86 25°C 88 25°C 78 25°C Rev Page AD9639BCPZ-210 Min Typ Max Unit 63.2 64.2 dB 63.2 dB 62.8 63 10.1 10.3 Bits 10.2 Bits 86 77 dBc 80 dBc 76 72.6 dBc 77 dBc 90 83.7 dBc 88 dBc 77 dBc ...
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... AVDD Full 0.2 × AVDD Full 0 Full −60 Full 55 Full 0 25°C 30 25°C 4 Full 1.2 AVDD + 0.3 Full 0 0.3 CML Full 0.8 Full DRVDD/2 Rev Page AD9639 AD9639BCPZ-210 Min Typ Max LVPECL/LVDS/CMOS 0.2 6 AVDD − AVDD + 0.3 1.6 1.2 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 + 0.8 × AVDD 0.2 × AVDD 0 − ...
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... Full 40 25°C 3.4 25°C 10 25°C 6 25°C 0 25°C ±1 25°C 50 25°C 100 25°C 1.2 25°C 0.2 25°C 1 Rev Page AD9639BCPZ-210 Min Typ Max Unit 100 210 MSPS 2.15 2.4 ns 2.15 2.4 ns 1/(20 × Seconds CLK μs 250 ns 50 μs ...
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... TIMING DIAGRAM N – – 39 ANALOG INPUT SIGNAL SAMPLE RATE CLOCK SAMPLE RATE CLOCK SERIAL DATA OUTPUT SAMPLE – – 37 ... SERIAL CODED SAMPLES: N – 40, N – 39, N – 38, N – 37 ... ... ... ... Figure 2. Timing Diagram Rev Page ... ... ... ... AD9639 ...
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... AD9639 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD DOUT + x/DOUT − DRGND SDO, SDI/SDIO, CLK±, VIN ± x, VCM x, TEMPOUT, RBIAS to AGND SCLK, CSB, PGMx, RESET, PDWN to AGND Storage Temperature Range Operating Temperature Range ...
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... Reset Enable Pin. Resets the digital output timing. Digital Output Driver Ground. 1.8 V Digital Output Driver Supply. ADC D Digital Output True. ADC D Digital Output Complement. ADC C Digital Output True. ADC C Digital Output Complement. ADC B Digital Output True. ADC B Digital Output Complement. Rev Page AD9639 PGM0 52 PGM1 51 PGM2 50 ...
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... AD9639 Pin No. Mnemonic 31 DOUT + A 32 DOUT − PDWN 37 SDO 38 SDI/SDIO 39 SCLK 40 CSB 44 VIN + A 45 VIN − VCM A 50, 51, 52, 53 PGM3, PGM2, PGM1, PGM0 56 VCM B 58 VIN − VIN + B 67 VIN + C 68 VIN − VCM C Description ADC A Digital Output True. ...
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... MHz SAMPLE 170MSPS 210MSPS 110 130 150 170 190 210 ENCODE (MSPS) Figure 8. SNR vs. Encode 84.3 MHz IN 170MSPS 210MSPS 110 130 150 170 190 210 ENCODE (MSPS) Figure 9. SFDR vs. Encode 84.3 MHz IN AD9639 100 = 210 MSPS 230 250 230 250 ...
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... AD9639 100 90 SFDR (dBFS) 80 SNR (dBFS SFDR (dB SNR (dB –90 –80 –70 –60 –50 –40 ANALOG INPUT LEVEL (dBFS) Figure 10. SNR/SFDR vs. Analog Input Level 84.3 MHz 100 90 SFDR (dBFS SNR (dBFS SFDR (dB SNR (dB –90 – ...
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... Figure 19. INL 9.7 MHz 210 MSPS IN SAMPLE 500 1000 1500 2000 2500 3000 3500 4000 CODE Figure 20. DNL 9.7 MHz 210 MSPS IN SAMPLE INPUT REFERRED NOISE: 0.72 LSB N – – – MORE BIN = 170 MSPS SAMPLE AD9639 4500 4500 ...
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... AD9639 40,000 INPUT REFERRED NOISE: 0.70 LSB 35,000 30,000 25,000 20,000 15,000 10,000 5000 0 N – – – BIN Figure 22. Input-Referred Noise Histogram –20 –40 –60 –80 –100 –120 FREQUENCY (Hz) Figure 23. Noise Power Ratio (NPR), f ...
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... Rev Page AVDD AVDD 250Ω SDI/SDIO 30kΩ Figure 30. Equivalent SDI/SDIO Input Circuit AVDD TEMPOUT Figure 31. Equivalent TEMPOUT Output Circuit 100Ω 175Ω RBIAS Figure 32. Equivalent RBIAS Input/Output Circuit 175Ω VCM x Figure 33. Equivalent VCM x Output Circuit AD9639 ...
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... AD9639 DRVDD 4mA R TERM V DOUT + x CM 4mA Figure 34. Equivalent Digital Output Circuit 4mA DOUT – x 4mA Rev Page AVDD SDO AVDD 345Ω Figure 35. Equivalent SDO Output Circuit ...
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... Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9639, the default input span is 1.25 V p-p. To configure the ADC for a different input span, see the V For the best performance, an input span of 1.25 V p-p or greater should be used (see Table 15 for details) ...
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... If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched to achieve the best possible performance. A full-scale input of 1.25 V p-p can be applied to the VIN + x pin of the AD9639 while the VIN − x pin is terminated. Figure 42 VIN + x ADC shows a typical single-ended input configuration. ...
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... This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally to 1.2 V and require no additional biasing. Figure 43 shows a preferred method for clocking the AD9639. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-to- back Schottky diodes across the secondary transformer limit clock excursions into the AD9639 to approximately 0 ...
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... Figure 48. Ideal SNR vs. Input Frequency and Jitter Power Dissipation As shown in Figure 49 and Figure 50, the power dissipated by ) the AD9639 is proportional to its clock rate. The digital power A dissipation does not vary significantly because it is determined primarily by the DRVDD supply and the bias current of the × ...
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... IEEE Std 802.3-2002, Section 3, for a complete 8B/10B and comma symbol description.) The 8B/10B encoding works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. In the AD9639, the 12-bit converter word is broken into two octets. Bit 11 through Bit 4 are in the first octet. The second octet contains Bit 3 through Bit 0 and four tail bits ...
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... AD9639 S15 LSB S31 D CLK S14 D S30 CLK S13 D S29 CLK S15 S12 D S28 CLK S14 S11 S27 D CLK S13 S10 D S26 CLK S12 S9 S25 D CLK S11 S8 D S24 MSB CLK S10 S7 LSB S23 D CLK S22 CLK S8 S5 S21 D CLK ...
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... The PGMx pins are used as SYNC pins by default. When the SYNC pin is taken low for at least two clock cycles, the AD9639 enters the synchronization mode. The AD9639 transmits the K28.5 comma symbol until the receiver can identify the frame boundary. ...
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... AD9639 Continuous Synchronization Continuous synchronization is part of the JESD204 specification. The 12-bit word requires two octets to transmit all the data. The two octets (MSB and LSB) are called a frame. When scrambling is disabled and the LSB octets of two consecutive frames are the same, the second LSB octet is replaced by a K28.7 comma symbol. ...
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... Digital Outputs and Timing The AD9639 has differential digital outputs that power up by default. The driver current is derived on chip and sets the output current at each output equal to a nominal 8 mA. Each output presents a 100 Ω dynamic internal termination to reduce unwanted reflections. ...
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... AD9639 HEIGHT1: EYE DIAGRAM (y1) –375.023m 600 (y2) +409.847m (Δy) +784.671m 400 200 0 –200 –400 EYE: ALL BITS OFFSET: 0.015 –600 ULS: 5000: 40044, TOTAL: 12000: 80091 –200 –100 0 100 TIME (ps) Figure 59. Digital Outputs Data Eye with Trace Lengths Less Than 6 Inches on Standard FR-4, External 100 Ω Terminations at Receiver ...
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... Section 5.6 of the ITU-T O.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 11 for the initial values) and that the AD9639 inverts the bit stream with relation to the ITU-T standard. Table 11. PN Sequence ...
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... When the PDWN pin is asserted high, the AD9639 is placed into power-down mode, shutting down the reference, reference buffer, PLL, and biasing networks. In this state, the ADC typically dissipates 3 mW ...
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... SERIAL PORT INTERFACE (SPI) The AD9639 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the ADC. The SPI can provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... AD9639 HIGH CSB DON’T SCLK CARE SDI/ DON’T R A12 SDIO CARE Table 14. Serial Timing Definitions Parameter Timing (ns min CLK HIGH t 16 LOW t 10 EN_SDI/SDIO t 10 DIS_SDI/SDIO 1.800 1 ...
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... Blank cells in Table 15 should be considered reserved bits and have a 0 written into their registers during power-up. DEFAULT VALUES When the AD9639 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 15. LOGIC LEVELS In Table 15, “ ...
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... Bit 5 Bit 4 Bit 3 Bit 2 Soft 16-bit reset address (default mode for ADCs) 8-bit chip ID, Bits[2:0] 0x0B: AD9639, 12-bit quad Speed grade 010 = 170 MSPS 100 = 210 MSPS ADC A ADC B Reset PN Reset PN Flexible output test mode sequence sequence 0000 = off (normal operation) ...
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... B10 B13 B12 B11 B10 B13 B12 B11 B10 Rev Page AD9639 Default (LSB) Value Bit 1 Bit 0 (Hex) Comments 0x00 Device offset trim. Data format select 0x00 Configures (global) the outputs 00 = offset binary and the (default) ...
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... AD9639 Addr. Register (MSB) (Hex) Name Bit 7 Bit 6 0x21 serial_control (global) 0x24 misr_lsb B7 B6 (local) 0x25 misr_msb B15 B14 (local) 0x33 JESD204 (global) 0x50 coarse_ Gain adjust gain_adj enable (local off (default) 0x51 fine_ gain_adj (local) 0x52 gain_cal_ctl Temperature sensor ...
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... ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9639. An exposed continuous copper plane on the PCB should mate to the AD9639 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB ...
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... AD9639BCPZRL-170 −40°C to +85°C 1 AD9639BCPZ-210 −40°C to +85°C 1 AD9639BCPZRL-210 −40°C to +85°C 1 AD9639-210KITZ RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...