AD9634BCPZRL7-250 Analog Devices, Inc., AD9634BCPZRL7-250 Datasheet
AD9634BCPZRL7-250
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AD9634BCPZRL7-250 Summary of contents
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... Fax: 781.461.3113 AD9634 AVDD AGND DRVDD PIPELINE 12 12-BIT ADC PARALLEL DDR LVDS AND DRIVERS 1-TO-8 SERIAL PORT CLOCK DIVIDER SDIO CSB CLK+ CLK– Figure 1. www.analog.com ©2011 Analog Devices, Inc. All rights reserved. D0±/D1± D10±/D11± DCO± OR± ...
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AD9634 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 ADC DC Specifications................................................................. 3 ADC AC Specifications ................................................................. 4 Digital Specifications ................................................................... ...
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SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, DCS enabled, unless otherwise noted. Table 1. Parameter Temperature RESOLUTION Full ACCURACY ...
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AD9634 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR ...
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Parameter TWO-TONE SFDR f = 184.1 MHz, 187.1 MHz (−7 dBFS FULL POWER BANDWIDTH 3 NOISE BANDWIDTH 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 ...
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AD9634 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal ...
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SWITCHING SPECIFICATIONS Table 4. Parameter 1 CLOCK INPUT PARAMETERS Input Clock Rate 2 Conversion Rate DCS Enabled DCS Disabled CLK Period, Divide-by-1 Mode (t ) CLK CLK Pulse Width High ( Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS ...
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AD9634 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments SPI TIMING REQUIREMENTS See Figure 58 for the SPI timing diagram t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND D0±/D1± through D10±/D11± to AGND DCO+/DCO− to ...
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AD9634 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE Table 8. Pin Function Descriptions Pin No. Mnemonic ADC Power ...
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Pin No. Mnemonic SPI Control 23 SCLK 22 SDIO 24 CSB Type Description Input SPI Serial Clock. Input/Output SPI Serial Data I/O. Input SPI Chip Select (Active Low). Rev Page AD9634 ...
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AD9634 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample 25°C, unless otherwise noted. ...
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SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) Figure 10. AD9634-170 Two-Tone SFDR/IMD3 vs. Input Amplitude ( ...
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AD9634 0 210MSPS 90.1MHz @ –1.0dBFS SNR = 69.1dB (70.1dBFS) –20 SFDR = 92dBc –40 –60 SECOND THIRD HARMONIC HARMONIC –80 –100 –120 –140 FREQUENCY (MHz) Figure 16. AD9634-210 Single-Tone FFT with f 0 210MSPS ...
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SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) Figure 22. AD9634-210 Two-Tone SFDR/IMD3 vs. Input Amplitude ( ...
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AD9634 0 250MSPS 90.1MHz @ –1.0dBFS SNR = 69.0dB (70.0dBFS) –20 SFDR = 89dBc –40 –60 SECOND THIRD HARMONIC HARMONIC –80 –100 –120 –140 FREQUENCY (MHz) Figure 28. AD9634-250 Single-Tone FFT with f 0 250MSPS 185.1MHz ...
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SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) Figure 34. AD9634-250 Two-Tone SFDR/IMD3 vs. Input Amplitude ( ...
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AD9634 EQUIVALENT CIRCUITS AVDD VIN Figure 40. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 41. Equivalent Clock lnput Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 42. Equivalent LVDS Output Circuit AVDD CLK– Rev. 0 ...
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THEORY OF OPERATION The AD9634 can sample any f /2 frequency segment from 250 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Programming and control of the AD9634 ...
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AD9634 Differential Input Configurations Optimum performance can be achieved when driving the AD9634 in a differential input configuration. For baseband applications, the AD8138, ADA4937-1, and differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode ...
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AD8375 NOTES 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS). 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. An alternative to using a transformer-coupled input at frequencies ...
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AD9634 A third option couple a differential LVDS signal to the sample clock input pins, as shown in Figure 55. The AD9510, AD9511,AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, AD9524 excellent jitter performance. 0.1µF ...
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POWER DISSIPATION AND STANDBY MODE As shown in Figure 57, the power dissipated by the proportional to its sample rate. The data in Figure 57 was taken using the same operating conditions as those used for the Typical Performance Characteristics ...
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AD9634 SERIAL PORT INTERFACE (SPI) The AD9634 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI offers added flexibility and customization, depending ...
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SPI ACCESSIBLE FEATURES Table 12 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in AN-877 Application Note, Interfacing to High Speed ADCs via S PI ...
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AD9634 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02), the ...
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MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 13 are not currently supported for this device. Table 13. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration Registers ...
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AD9634 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST enable Open Open 0x10 Offset adjust Open Open 0x14 Output mode Open Open 0x15 Output adjust Open Open 0x16 Clock phase Invert Open control DCO clock 0x17 Open ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system-level design and layout of the AD9634 recommended that the designer become familiar with these guidelines, which describe the special circuit connections and layout requirements needed for certain pins. Power and Ground ...
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... INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9634BCPZ-250 −40°C to +85°C AD9634BCPZRL7-250 −40°C to +85°C AD9634BCPZ-210 −40°C to +85°C AD9634BCPZRL7-210 −40°C to +85°C AD9634BCPZ-170 −40°C to +85°C AD9634BCPZRL7-170 −40°C to +85°C AD9634-170EBZ AD9634-210EBZ AD9634-250EBZ RoHS Compliant Part ...
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NOTES Rev Page AD9634 ...
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... AD9634 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09996-0-7/11(0) Rev Page ...