AD9642BCPZRL7-250 Analog Devices, Inc., AD9642BCPZRL7-250 Datasheet

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AD9642BCPZRL7-250

Manufacturer Part Number
AD9642BCPZRL7-250
Description
14-bit, 170 Msps/210 Msps/250 Msps, 1.8 V Analog-to-digital Converter Adc
Manufacturer
Analog Devices, Inc.
Datasheet
FEATURES
SNR = 71.0 dBFS at 185 MHz A
SFDR = 83 dBc at 185 MHz A
−152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS A
Total power consumption: 390 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 350 MHz
Internal ADC voltage reference
Flexible analog input range
ADC clock duty cycle stabilizer
Serial port control
Energy saving power-down modes
User-configurable, built-in self-test (BIST) capability
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, WCDMA,
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The
sampling speeds of up to 250 MSPS. The
support communications applications, where low cost, small
size, wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs that can support a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty
cycle, allowing the converter to maintain excellent performance.
The ADC output data is routed directly to the external
14-bit LVDS output port.
Flexible power-down options allow significant power savings,
when desired.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
CDMA2000, GSM, EDGE, LTE
AD9642
is a 14-bit analog-to-digital converter (ADC) with
IN
and 250 MSPS
IN
and 250 MSPS
AD9642
is designed to
IN
, 250 MSPS
1.8 V Analog-to-Digital Converter (ADC)
14-Bit, 170 MSPS/210 MSPS/250 MSPS,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Programming for setup and control is accomplished using a
3-wire SPI-compatible serial interface.
The
over the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
VIN+
VIN–
VCM
AD9642
Integrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating LVDS outputs.
Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 350 MHz.
3-pin, 1.8 V SPI port for register programming and readback.
Pin compatibility with the AD9634, allowing a simple migra-
tion from 14 bits to 12 bits, and with the AD6672.
REFERENCE
AD9642
SCLK
FUNCTIONAL BLOCK DIAGRAM
SERIAL PORT
is available in a 32-lead LFCSP and is specified
SDIO
AVDD
PIPELINE
14-BIT
ADC
©2011 Analog Devices, Inc. All rights reserved.
CSB
AGND
14
Figure 1.
CLK+
PARALLEL
DDR LVDS
DRIVERS
DIVIDER
CLOCK
1-TO-8
AND
DRVDD
CLK–
AD9642
www.analog.com
D0±/D1±
D12±/D13±
DCO±

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AD9642BCPZRL7-250 Summary of contents

Page 1

... AD9642 PARALLEL DDR LVDS AND DRIVERS REFERENCE 1-TO-8 SERIAL PORT CLOCK DIVIDER SCLK SDIO CSB CLK+ CLK– Figure 1. is available in a 32-lead LFCSP and is specified ©2011 Analog Devices, Inc. All rights reserved. D0±/D1± D12±/D13± DCO± www.analog.com ...

Page 2

AD9642 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 ADC DC Specifications ............................................................... 3 ADC AC Specifications ............................................................... 4 Digital Specifications ...

Page 3

SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 1. Parameter Temperature RESOLUTION Full ACCURACY No ...

Page 4

AD9642 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR ...

Page 5

Parameter 2 FULL POWER BANDWIDTH NOISE BANDWIDTH 3 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Full power bandwidth is the bandwidth of operation where typical ADC ...

Page 6

AD9642 SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate 1 Conversion Rate CLK Period—Divide-by-1 Mode (t ) CLK CLK Pulse Width High ( Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode Through Divide-by-8 ...

Page 7

TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments SPI TIMING REQUIREMENTS See Figure 58 for SPI timing diagram t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge ...

Page 8

AD9642 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND D0−/D1−, D0+/D1+ Through D12−/D13−, D12+/D13+ to ...

Page 9

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions Pin No. Mnemonic ADC Power Supplies 8, 17 DRVDD 3, 27, 28, 31, 32 AVDD 0 AGND, Exposed Paddle 25 DNC ADC Analog 30 VIN+ 29 VIN− 26 VCM 1 ...

Page 10

AD9642 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample 25°C, unless otherwise noted. A ...

Page 11

SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) Figure 10. AD9642-170 Two-Tone SFDR/IMD3 vs. Input Amplitude ( ...

Page 12

AD9642 0 210MSPS 90.1MHz @ –1dBFS –20 SNR = 71.2dB (72.2dBFS) SFDR = 92dBc –40 –60 THIRD HARMONIC –80 SECOND HARMONIC –100 –120 –140 FREQUENCY (MHz) Figure 16. AD9642-210 Single-Tone FFT with f 0 210MSPS ...

Page 13

SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) Figure 22. AD9642-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f ...

Page 14

AD9642 0 250MSPS 90.1MHz @ –1dBFS –20 SNR = 71dB (72dBFS) SFDR = 89dBc –40 THIRD HARMONIC –60 SECOND HARMONIC –80 –100 –120 –140 FREQUENCY (MHz) Figure 28. AD9642-250 Single-Tone FFT with f 0 250MSPS 185.1MHz ...

Page 15

SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) Figure 34. AD9642-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f ...

Page 16

AD9642 EQUIVALENT CIRCUITS AVDD VIN Figure 40. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 41. Equivalent Clock Input Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 42. Equivalent LVDS Output Circuit AVDD CLK– Rev. 0 ...

Page 17

THEORY OF OPERATION The AD9642 can sample any f /2 frequency segment from 250 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Programming and control of the AD9642 ...

Page 18

AD9642 For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 48. To bias the analog input, connect the VCM voltage to the center tap of the ...

Page 19

VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9642. The full-scale input range can be adjusted by varying the reference voltage via SPI. The input span of the ADC tracks reference voltage changes linearly. CLOCK INPUT ...

Page 20

AD9642 cycle control loop does not function for clock rates less than 40 MHz nominally. The loop has a time constant associated with it that must be considered when the clock rate may change dynamically. A wait time of 1.5 ...

Page 21

Timing The AD9642 provides latched data with a pipeline delay of 10 input sample clock cycles. Data outputs are available one propagation delay (t ) after the rising edge of the clock signal. PD Minimize the length of the output ...

Page 22

AD9642 SERIAL PORT INTERFACE (SPI) The AD9642 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI offers added flexibility and customization, depending ...

Page 23

SPI ACCESSIBLE FEATURES Table 12 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Table 12. Features ...

Page 24

AD9642 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the ...

Page 25

MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 13 are not currently supported for this device. Table 13. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration Registers ...

Page 26

AD9642 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST enable Open Open 0x10 Offset adjust Open Open 0x14 Output mode Open Open 0x15 Output adjust Open Open 0x16 Clock phase Invert Open control DCO clock 0x17 DCO ...

Page 27

APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system level design and layout of the AD9642 recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements for certain pins. Power and Ground ...

Page 28

... AD9642BCPZ-210 −40°C to +85°C AD9642BCPZ-250 −40°C to +85°C AD9642BCPZRL7-170 −40°C to +85°C AD9642BCPZRL7-210 −40°C to +85°C AD9642BCPZRL7-250 −40°C to +85°C AD9642-170EBZ −40°C to +85°C AD9642-210EBZ −40°C to +85°C AD9642-250EBZ −40°C to +85° RoHS Compliant Part. © ...

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