IC FLIP FLOP DUAL DTYPE 14TSSOP

74LVX74MTCX

Manufacturer Part Number74LVX74MTCX
DescriptionIC FLIP FLOP DUAL DTYPE 14TSSOP
ManufacturerFairchild Semiconductor
Series74LVX
TypeD-Type
74LVX74MTCX datasheet
 


Specifications of 74LVX74MTCX

FunctionSet(Preset) and ResetOutput TypeDifferential
Number Of Elements2Number Of Bits Per Element1
Frequency - Clock95MHzDelay Time - Propagation5.7ns
Trigger TypePositive EdgeCurrent - Output High, Low4mA, 4mA
Voltage - Supply2 V ~ 3.6 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case14-TSSOP
Dc1049Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names74LVX74MTCXTR  
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74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
Features
Input voltage level translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Information
Order
Package
Number
Number
74LVX74M
M14A
74LVX74SJ
M14D
74LVX74MTC
MTC14
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1993 Fairchild Semiconductor Corporation
74LVX74 Rev. 1.4.0
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on
the positive edge of the clock pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to S
LOW input to C
Clear and Set are independent of clock
Simultaneous LOW on C
Q HIGH
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
February 2008
(Set) sets Q to HIGH level
D
(Clear) sets Q to LOW level
D
and S
makes both Q and
D
D
www.fairchildsemi.com

74LVX74MTCX Summary of contents

  • Page 1

    ... MTC14 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 General Description The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs ...

  • Page 2

    ... Connection Diagram Pin Description Pin Names Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 Logic Symbols IEEE/IEC Truth Table (Each Half) Inputs HIGH Voltage Level L LOW Voltage Level X Immaterial ...

  • Page 3

    ... Input Voltage I V Output Voltage O T Operating Temperature Input Rise and Fall Time Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 Parameter –0.5V I (1) Parameter 3 Rating –0.5V to +7.0V –20mA –0. –20mA +20mA – ...

  • Page 4

    ... Quiet Output Minimum Dynamic V OLV V Minimum HIGH Level Dynamic Input Voltage IHD V Maximum LOW Level Dynamic Input Voltage ILD Note: 2. Input t t 3ns r f ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 V Conditions Min. Typ. Max. CC 2.0 3.0 3.6 2.0 3.0 3.6 2.0 V ...

  • Page 5

    ... Input Capacitance IN C Power Dissipation Capacitance PD Note defined as the value of the internal equivalent capacitance which is calculated from the operating current PD consumption without load. Average operating current can be obtained by the eqation: I ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 V (V) C (pF) Min 2 3.3 ± ...

  • Page 6

    ... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

  • Page 7

    ... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

  • Page 8

    ... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

  • Page 9

    ... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...