IC F/F DL D POS EDGE TRIG 14-DIP

74F74PC

Manufacturer Part Number74F74PC
DescriptionIC F/F DL D POS EDGE TRIG 14-DIP
ManufacturerFairchild Semiconductor
Series74F
TypeD-Type
74F74PC datasheet
 


Specifications of 74F74PC

FunctionSet(Preset) and ResetOutput TypeDifferential
Number Of Elements2Number Of Bits Per Element1
Frequency - Clock125MHzDelay Time - Propagation5.3ns
Trigger TypePositive EdgeCurrent - Output High, Low1mA, 20mA
Voltage - Supply4.5 V ~ 5.5 VOperating Temperature0°C ~ 70°C
Mounting TypeThrough HolePackage / Case14-DIP (0.300", 7.62mm)
Number Of Circuits2Logic Family74F
Logic TypeD-Type Edge Triggered Flip-FlopPolarityInverting/Non-Inverting
Input TypeSingle-EndedPropagation Delay Time8 ns
High Level Output Current- 1 mALow Level Output Current20 mA
Supply Voltage (max)5.5 VMaximum Operating Temperature+ 70 C
Mounting StyleThrough HoleMinimum Operating Temperature0 C
Supply Voltage (min)4.5 VLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names74F74  
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74F74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The F74 is a dual D-type flip-flop with Direct Clear and Set
inputs and complementary (Q, Q) outputs. Information at
the input is transferred to the outputs on the positive edge
of the clock pulse. Clock triggering occurs at a voltage level
of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
Ordering Code:
Order Number
Package Number
74F74SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F74PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to S
sets Q to HIGH level
D
LOW input to C
sets Q to LOW level
D
Clear and Set are independent of clock
Simultaneous LOW on C
D
makes both Q and Q HIGH
Package Description
Connection Diagram
DS009469
April 1988
Revised September 2000
and S
D
www.fairchildsemi.com

74F74PC Summary of contents

  • Page 1

    ... Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

  • Page 2

    Unit Loading/Fan Out Pin Names Data Inputs Clock Pulse Inputs (Active Rising Edge Direct Clear Inputs (Active LOW Direct Set Inputs (Active ...

  • Page 3

    Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

  • Page 4

    AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH PHL Propagation Delay PLH PHL ...

  • Page 5

    Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 5 www.fairchildsemi.com ...

  • Page 6

    Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M14D 6 ...

  • Page 7

    Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...