TS80C52zzz-MIC Atmel Corporation, TS80C52zzz-MIC Datasheet

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TS80C52zzz-MIC

Manufacturer Part Number
TS80C52zzz-MIC
Description
8-bit Microcontroller 8 Kbytes ROM/OTP, ROMless
Manufacturer
Atmel Corporation
Datasheet
Features
Description
TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions
of the 80C51 CMOS single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the 80C51 with extended ROM/EPROM
capacity (8 Kbytes), 256 bytes of internal RAM, a 6-source, 4-level interrupt system,
an on-chip oscilator and three timer/counters.
In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and an X2 speed improve-
ment mechanism.
The fully static design of the TS80C52X2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The TS80C52X2 has 2 software-selectable modes of reduced activity for further
reduction in power consumption. In the idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
80C52 Compatible
High-speed Architecture
40 MHz at 5V, 30 MHz at 3V
X2 Speed Improvement Capability (6 Clocks/Machine Cycle)
Dual Data Pointer
On-chip ROM/EPROM (8Kbytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Asynchronous Port Reset
Interrupt Structure with
Full Duplex Enhanced UART
Low EMI (Inhibit ALE)
Power Control Modes
Once Mode (On-chip Emulation)
Power Supply: 4.5 - 5.5V, 2.7 - 5.5V
Temperature Ranges: Commercial (0 to 70
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 (13.9 footprint)
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/Counters
– 256 Bytes Scratchpad RAM
– 30 MHz at 5V, 20 MHz at 3V (Equivalent to 60 MHz at 5V, 40 MHz at 3V)
– 6 Interrupt Sources
– 4 Level Priority Interrupt System
– Framing Error Detection
– Automatic Address Recognition
– Idle Mode
– Power-down Mode
– Power-off Flag
o
C) and Industrial (-40 to 85
o
C)
8-bit
Microcontroller
8 Kbytes
ROM/OTP,
ROMless
TS80C32X2
TS87C52X2
TS80C52X2
Rev. 4184E–8051–09/02

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TS80C52zzz-MIC Summary of contents

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Features • 80C52 Compatible – 8051 Pin and Instruction Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratchpad RAM • High-speed Architecture • 40 MHz at 5V, 30 MHz at 3V • X2 Speed Improvement ...

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Block Diagram TS8xCx2X2 2 Table 1. Memory Size ROM (bytes) TS80C32X2 0 TS80C52X2 8k TS87C52X2 0 (3) (3) XTAL1 EUART XTAL2 ALE/ PROG PSEN CPU EA/VPP (2) Timer 0 RD Timer 1 (2) WR (2) (2) Notes: 1. Alternate function ...

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SFR Mapping 4184E–8051–09/02 The Special Function Registers (SFRs) of the TS80C52X2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3 • Timer registers: T2CON, T2MOD, ...

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Table 2. All SFRs with their address and their reset value Bit Addressable 0/8 1/9 F8h B F0h 0000 0000 E8h ACC E0h 0000 0000 PSW h 0000 0000 C8 T2CON T2MOD h 0000 0000 XXXX XX00 ...

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Pin Configuration P1 P1.1 / T2EX 2 P1.2 3 P1.3 4 P1.4 5 P1 P1.7 RST 9 P3.0/RxD 10 PDIL/ P3.1/TxD 11 12 CDIL40 P3.2/INT0 P3.3/INT1 13 P3.4/ P3.5/T1 P3.6/WR 16 ...

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TS8xCx2X2 6 Mnemonic Pin Number Type Name and Function VQFP DIL LCC 1 Vss1 39- 43- P0.0-P0.7 37-30 I P1.0-P1.7 1-8 2-9 40-44 I/O 1-3 1 ...

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Mnemonic Pin Number Type Name and Function VQFP DIL LCC 1 Reset ALE/PROG (I) Address ...

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TS80C52X2 Enhanced Features X2 Feature Description TS8xCx2X2 8 In comparison to the original 80C52, the TS80C52X2 implements some new features, which are : • The X2 option • The Dual Data Pointer • The 4 level interrupt priority system • ...

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Figure 2. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode 4184E–8051–09/02 X2 Mode The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and ...

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Dual Data Pointer Register (Ddptr) Figure 3. Use of Dual Pointer 7 0 DPS AUXR1(A2H) TS8xCx2X2 10 The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual ...

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Application 4184E–8051–09/02 Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and ...

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Timer 2 Auto-reload Mode TS8xCx2X2 12 TS80C52X2 The timer 2 in the is compatible with the timer 2 in the 80C52 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in ...

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Figure 4. Auto-reload Mode Up/Down Counter (DCEN = 1) XTAL1 F XTAL Programmable Clock-output 4184E–8051–09/02 (: mode) :12 F OSC T2 C/T2 T2CONreg (DOWN COUNTING RELOAD FFh (8-bit) TL2 (8-bit) RCAP2L RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) In ...

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Figure 5. Clock-Out Mode C/ XTAL1 T2 T2EX TS8xCx2X2 mode) TR2 T2CON reg TL2 (8-bit) RCAP2L (8-bit) Toggle Q D T2MOD reg EXF2 T2CON reg EXEN2 T2CON reg TH2 (8-bit) OVERFLOW RCAP2H (8-bit) ...

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Table 5. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 ...

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TS8xCx2X2 16 Table 6. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this ...

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TS80C52X2 Serial I/O Port Framing Error Detection Figure 6. Framing Error Block Diagram SM0/FE SMOD1 Figure 7. UART Timings in Mode 1 RXD RI SMOD0=X FE SMOD0=1 4184E–8051–09/02 The serial I/O port in the TS80C52X2 is compatible with the serial ...

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Figure 8. UART Timings in Modes 2 and 3 RXD RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Automatic Address Recognition Given Address TS8xCx2X2 Start Data byte bit The automatic address recognition feature is enabled when ...

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Broadcast Address Reset Addresses 4184E–8051–09/02 1111 0000b). For slave A, bit for slaves B and C, bit don’t care bit. To communicate with slaves B and C, but not slave A, the master ...

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TS8xCx2X2 20 Table 9. SCON Register SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. ...

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Table 10. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...

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Interrupt System Figure 9. Interrupt Control System INT0 TF0 INT1 TF1 RI TI TF2 EXF2 Individual Enable TS8xCx2X2 22 The TS80C52X2 has a total of 6 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 ...

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Thus within each priority level there is a second priority structure determined by the polling sequence. Table 12. IE Register IE - Interrupt Enable Register (A8h) 7 ...

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TS8xCx2X2 24 Table 13. IP Register IP - Interrupt Priority Register (B8h PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

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Table 14. IPH Register IPH - Interrupt Priority High Register (B7h PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

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Idle mode Power-down Mode Figure 10. Power-down Exit Waveform INT0 INT1 XTAL1 Active phase TS8xCx2X2 26 An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the ...

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Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content. Note: If idle ...

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TM ONCE Mode (ON Chip Emulation) TS8xCx2X2 28 The ONCE mode facilitates testing and debugging of systems using TS80C52X2 with- out removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C52X2; the ...

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Power-off Flag 4184E–8051–09/02 The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced still applied to the device and could ...

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Reduced EMI Mode TS8xCx2X2 30 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to ...

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TS80C52X2 ROM Structure ROM Lock System Encryption Array Program Lock Bits Signature bytes Verify Algorithm 4184E–8051–09/02 The TS80C52X2 ROM memory is divided in three different arrays: • the code array:8 Kbytes. • the encryption array:64 bytes. • the signature array:4 ...

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TS87C52X2 EPROM Structure EPROM Lock System Encryption Array Program Lock Bits Signature Bytes TS8xCx2X2 32 The TS87C52X2 is divided in two different arrays: • the code array: 8 Kbytes • the encryption array: 64 bytes In addition a third non ...

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EPROM Programming Set-up modes Definition of terms 4184E–8051–09/02 In order to program and verify the EPROM or to read the signature bytes, the TS87C52X2 is placed in specific set-up modes (See Figure 11.). Control and program signals must be held ...

Page 34

Figure 11. Set-Up Modes Configuration PROGRAM SIGNALS* CONTROL SIGNALS MHz * See Table 31. for proper value on these inputs Programming Algorithm Verify Algorithm TS8xCx2X2 34 EA/VPP ALE/PROG P0.0-P0.7 RST PSEN P1.0-P1.7 P2.6 P2.7 P2.0-P2.4 P3.3 P3.6 ...

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Figure 12. Programming and Verification Signal’s Waveform A0-A12 D0-D7 ALE/PROG 12.75V 5V EA/VPP 0V Control signals EPROM Erasure (Windowed Packages Only) Erasure Characteristics Signature Bytes 4184E–8051–09/02 Programming Cycle Data In 100µs Erasing the EPROM erases the code array, the encryption ...

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Electrical Characteristics Absolute Maximum (1) Ratings Ambiant Temperature Under Bias commercial......................................................0°C to 70° industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65° 150°C Voltage .........................................-0. ...

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Table 22. DC Parameters in Standard Voltage (Continued) Symbol Parameter V Output High Voltage, ports Output High Voltage, port 0 OH1 V Output High Voltage,ALE, PSEN OH2 R RST Pulldown Resistor RST I Logical 0 ...

Page 38

DC Parameters for Low Voltage Table 23. DC Parameters for Low Voltage Symbol Parameter V Input Low Voltage IL V Input High Voltage except XTAL1, RST IH V Input High Voltage, XTAL1, RST IH1 V Output Low Voltage, ports 1, ...

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Port Ports 1, 2 and Maximum total I for all output pins exceeds the test condition than the listed test conditions. 7. For other values, please contact ...

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Figure 16. I Test Condition, Power-down Mode CC Reset = Vss after a high pulse during at least 24 clock cycles Figure 17. Clock Signal Waveform for I AC Parameters Explanation of the AC Symbols TS8xCx2X2 ...

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External Program Memory Characteristics 4184E–8051–09/02 Table 28., Table 31. and Table 34. give the frequency derating formula of the AC param- eter. To calculate each AC symbols, take the x value corresponding to the speed grade you need (-M, -V ...

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TS8xCx2X2 42 Table 27. AC Parameters for Fix Clock -V X2 mode 30 MHz -M 60 MHz Speed 40 MHz equiv. Symbol Min Max Min LHLL AVLL LLAX ...

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External Program Memory Read Cycle Figure 18. External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 External Data Memory Characteristics 4184E–8051–09/ CLCL T T LHLL LLIV T LLPL T PLPH T ...

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TS8xCx2X2 44 Table 30. AC Parameters for a Fix Clock -V X2 mode 30 MHz Speed -M 60 MHz 40 MHz equiv. Symbol Min Max Min T 130 85 RLRH T 130 85 WLWH T 100 RLDV ...

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External Data Memory Write Cycle Figure 19. External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 4184E–8051–09/02 Table 31. AC Parameters for a Variable Clock: Derating Formula Standard Symbol Type Clock T Min 6 ...

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External Data Memory Read Cycle Figure 20. External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode TS8xCx2X2 46 T LLDV T LLWL T RLDV T AVDV T ...

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Shift Register Timing Waveforms Figure 21. Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 4184E–8051–09/02 Table 34. AC Parameters for a Variable Clock: Derating Formula Standard Symbol Type Clock ...

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EPROM Programming and Verification Characteristics EPROM Programming and Verification Waveforms Figure 22. EPROM Programming and Verification Waveforms P1.0-P1.7 P2.0-P2.5 P3.4-P3. ALE/PROG EA CONTROL SIGNALS (ENABLE) * 8KB P2.4, 16KB P2.5, 32KB: ...

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External Clock Drive Characteristics (XTAL1) External Clock Drive Waveforms Figure 23. External Clock Drive Waveforms VCC-0.5V 0.45V AC Testing Input/Output Waveforms Figure 24. AC Testing Input/Output Waveforms INPUT/OUTPUT Float Waveforms Figure 25. Float Waveforms 4184E–8051–09/02 Table 36. AC Parameters Symbol ...

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Clock Waveforms Figure 26. Clock Waveforms STATE4 INTERNAL CLOCK P1P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN DATA P0 SAMPLED FLOAT INDICATES ADDRESS TRANSITIONS P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV DEST ...

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... TS80C32X2-LIED ROMLess TS80C32X2-EDA ROMLess TS80C32X2-EDB ROMLess TS80C32X2-EDC ROMLess TS80C32X2-EDED ROMLess TS80C52zzz-MCA 8K ROM TS80C52zzz-MCB 8K ROM TS80C52zzz-MCC 8K ROM TS80C52zzz-VCA 8K ROM 4184E–8051–09/02 Temperature Supply Voltage Range Max Frequency 5V ±10 70°C 5V ±10 70°C 5V ±10 70°C 5V ±10 70°C 5V ±10 70°C 5V ± ...

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... Part Number Memory Size TS80C52zzz-VCB 8K ROM TS80C52zzz-VCC 8K ROM TS80C52zzz-VCED 8K ROM TS80C52zzz-LCA 8K ROM TS80C52zzz-LCB 8K ROM TS80C52zzz-LCC 8K ROM TS80C52zzz-LCED 8K ROM TS80C52zzz-MIA 8K ROM TS80C52zzz-MIB 8K ROM TS80C52zzz-MIC 8K ROM TS80C52zzz-VIA 8K ROM TS80C52zzz-VIB 8K ROM TS80C52zzz-VIC 8K ROM TS80C52zzz-VIED 8K ROM TS80C52zzz-LIA 8K ROM TS80C52zzz-LIB 8K ROM TS80C52zzz-LIC 8K ROM TS80C52zzz-LIED 8K ROM TS80C52zzz-EDA 8K ROM ...

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Table 37. Possible Ordering Entries (Continued) Part Number Memory Size TS87C52-MIA 8K OTP TS87C52-MIB 8K OTP TS87C52-MIC 8K OTP TS87C52-VIA 8K OTP TS87C52-VIB 8K OTP TS87C52-VIC 8K OTP TS87C52-VIED 8K OTP TS87C52-LIA 8K OTP TS87C52-LIB 8K OTP TS87C52-LIC 8K OTP ...

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... Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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