TS80C54X2YYY-MICD Atmel Corporation, TS80C54X2YYY-MICD Datasheet

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TS80C54X2YYY-MICD

Manufacturer Part Number
TS80C54X2YYY-MICD
Description
8-bit CMOS Microcontroller 16/32 Kbytes ROM/OTP
Manufacturer
Atmel Corporation
Datasheet
8-bit CMOS Microcontroller 16/32 Kbytes ROM/OTP
1. Description
and EPROM versions of the 80C51 CMOS single chip
8-bit microcontroller.
The TS80C54/58X2 retains all features of the Atmel
Wireless & Microcontrollers
ROM/EPROM capacity (16/32 Kbytes), 256 bytes of
internal RAM, a 6-source , 4-level interrupt system, an
on-chip oscilator and three timer/counters.
In addition, the TS80C54/58X2 has a Hardware
Watchdog Timer, a more versatile serial channel that
facilitates multiprocessor communication (EUART) and
a X2 speed improvement mechanism.
2. Features
Rev. C - 15 January, 2001
TS80C54/58X2 is high performance CMOS ROM, OTP
80C52 Compatible
High-Speed Architecture
Dual Data Pointer
On-chip ROM/EPROM (16K-bytes, 32K-bytes)
Programmable Clock Out and Up/Down Timer/
Counter 2
Hardware Watchdog Timer (One-time enabled with
Reset-Out)
Asynchronous port reset
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
80C51 with extended
The fully static design of the TS80C54/58X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C54/58X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
Interrupt Structure with
Full duplex Enhanced UART
Low EMI (inhibit ALE)
Power Control modes
Once mode (On-chip Emulation)
Power supply: 4.5-5.5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
Industrial (-40 to 85
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44
F1, CQPJ44 (window), CDIL40 (window)
6 Interrupt sources
4 level priority interrupt system
Framing error detection
Automatic address recognition
Idle mode
Power-down mode
Power-off Flag
TS80C54X2/C58X2
TS87C54X2/C58X2
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TS80C54X2YYY-MICD Summary of contents

Page 1

CMOS Microcontroller 16/32 Kbytes ROM/OTP 1. Description TS80C54/58X2 is high performance CMOS ROM, OTP and EPROM versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C54/58X2 retains all features of the Atmel Wireless & Microcontrollers 80C51 with extended ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 PDIL40 PLCC44 PQFP44 F1 VQFP44 1.4 TS80C54X2 TS80C58X2 TS87C54X2 TS87C58X2 3. Block Diagram (2) XTAL1 XTAL2 ALE/ PROG PSEN CPU EA/V PP (2) RD (2) WR (2) (2) 2 Table 1. Memory size ROM (bytes) 16k 32k 0 ...

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SFR Mapping The Special Function Registers (SFRs) of the TS80C54/58X2 fall into the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P0, P1, P2, P3 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 5. Pin Configuration P1 P1.1 / T2EX 38 P1 P1.7 RST 9 32 P3.0/RxD 10 31 PDIL/ ...

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Table 3. Pin Description for 40/44 pin packages PIN NUMBER MNEMONIC DIL LCC VQFP 1 Vss1 P0.0-P0.7 39-32 43-36 37-30 P1.0-P1.7 1-8 2-9 40-44 1 ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 Table 3. Pin Description for 40/44 pin packages PIN NUMBER MNEMONIC ALE/PROG PSEN EA XTAL1 XTAL2 TYPE NAME AND FUNCTION O ...

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TS80C54/58X2 Enhanced Features In comparison to the original 80C52, the TS80C54/58X2 implements some new features, which are The X2 option. The Dual Data Pointer. The Watchdog. The 4 level interrupt priority system. The power-off flag. The ONCE mode. The ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 XTAL1 XTAL1:2 X2 bit CPU clock STD Mode The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard ...

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CKCON - Clock Control Register (8Fh Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 6.2 Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip ...

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Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; ...

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Timer 2 TS80C54/58X2 The timer 2 in the 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade controlled by T2CON register (See Table 6) and T2MOD ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 XTAL1 F XTAL Figure 4. Auto-Reload Mode Up/Down Counter (DCEN = 1) 6.3.2 Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 5) . The input clock increments TL2 at ...

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It is possible to use timer baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 ...

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T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 6.4 TS80C54/58X2 Serial I/O Port The serial I/O port in the TS80C54/58X2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and ...

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Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 6.4.3 Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits ...

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Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit Set by hardware when ...

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PCON - Power Control Register (87h SMOD1 SMOD0 Bit Bit Number Mnemonic Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode Serial port Mode bit 0 6 SMOD0 ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 6.5 Interrupt System The TS80C54/58X2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown in Figure 9. ...

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IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 IP - Interrupt Priority Register (B8h PT2 Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from ...

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IPH - Interrupt Priority High Register (B7h PT2H Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 6.6 Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not ...

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Table 14. The state of ports during idle and power-down modes Program Mode ALE Memory Idle Internal Idle External Power Down Internal Power Down External * Port 0 can force a "zero" level. A "one" Level will leave port floating. ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 6.8 Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The ...

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WDTPRG Address (0A7h Bit Bit Number Mnemonic Reserved not try to set or clear this bit WDT Time-out select bit 2 1 ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 TM 6.9 ONCE Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C54/58X2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C54/58X2; the ...

Page 33

Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by V the device and could be generated for example by ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 6.11 Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order ...

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TS80C54/58X2 ROM 7.1 ROM Structure The TS80C54/58X2 ROM memory is in three different arrays: the code array ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 8. TS87C54/58X2 EPROM 8.1 EPROM Structure The TS87C54/58X2 EPROM is divided in two different arrays: the code array ...

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Signature bytes The TS87C54/58X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 8.3. 8.3 EPROM Programming 8.3.1 Set-up modes In order to program and verify the EPROM or to read the ...

Page 38

TS80C54X2/C58X2 TS87C54X2/C58X2 PROGRAM SIGNALS* CONTROL SIGNALS MHz * See Table 31. for proper value on these inputs 8.3.3 Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of ...

Page 39

Programming Cycle A0-A12 D0-D7 ALE/PROG 12.75V 5V EA/VPP 0V Control sig- nals Figure 12. Programming and Verification Signal’s Waveform 8.4 EPROM Erasure (Windowed Packages Only) Erasing the EPROM erases the code array, the encryption array and the lock bits returning ...

Page 40

TS80C54X2/C58X2 TS87C54X2/C58X2 9. Signature Bytes The has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the TS87C54/58X2 procedure for EPROM verify but activate the control lines provided in Table 31. for Read Signature ...

Page 41

Electrical Characteristics 10.1 Absolute Maximum Ratings Ambiant Temperature Under Bias commercial I = industrial Storage Temperature Voltage Voltage Voltage on Any Pin ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 10.3 DC Parameters for Standard Voltage + - + Table 24. DC Parameters ...

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Symbol Parameter I Power Supply Current Maximum values (7) mode: operating I Power Supply Current Maximum values (7) mode: idle 10.4 DC Parameters for Low Voltage + ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 Symbol Parameter I Power Supply Current Maximum values (7) mode: idle NOTES 1. I under reset is measured with all output pins disconnected; XTAL1 driven with 0.5V; XTAL2 N.C.; EA ...

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Reset = Vss after a high pulse during at least 24 clock cycles Reset = Vss after a high pulse during at least 24 clock cycles Reset = Vss after a high pulse during at least 24 clock cycles Figure ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 10.5 AC Parameters 10.5.1 Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a ...

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External Program Memory Characteristics Symbol T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL T ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 Table 30. AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock T Min LHLL T Min AVLL T Min LLAX T Max ...

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External Data Memory Characteristics Symbol T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ T ALE to Valid Data ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 Table 32. AC Parameters for a Fix Clock Speed -M 40 MHz Symbol Min Max T 130 RLRH T 130 WLWH T 100 RLDV T 0 RHDX T 30 RHDZ T 160 LLDV T 165 AVDV T 50 ...

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Table 33. AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock T Min RLRH T Min WLWH T Max RLDV T Min x RHDX T ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 10.5.6 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Figure 20. External Data Memory Read Cycle 10.5.7 Serial Port Timing - Shift Register Mode Symbol T XLXL T QVHX T XHQX ...

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Table 36. AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock T Min 12 T XLXL T Min QVHX T Min XHQX T Min x XHDX T Max 10 ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 10.5.9 EPROM Programming and Verification Characteristics 0V Table 37. EPROM Programming Parameters Symbol Parameter V Programming Supply Voltage PP I Programming Supply Current PP 1/T Oscillator ...

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External Clock Drive Characteristics (XTAL1) Symbol Parameter T Oscillator Period CLCL T High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL T /T Cyclic ratio in X2 mode CHCX CLCX 10.5.12 External Clock ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V 10.5.15 Clock Waveforms Valid in normal ...

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... VCC: 2 MHz, X1 mode 20 MHz, X2 mode -E: Samples Part Number TS80C54X2yyy: 16k ROM, yyy is the customer code TS80C58X2yyy: 32k ROM, yyy is the customer code TS87C54X2: 16k OTP EPROM TS87C58X2: 32k OTP EPROM (*) Check with Atmel Wireless & Microcontrollers Sales Office for availability. Ceramic packages (J, K) are available for proto- typing, not for volume production ...

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TS80C54X2/C58X2 TS87C54X2/C58X2 -MCA -MCB -MCC -MCE -VCA -VCB -VCC -VCE -LCA -LCB -LCC -LCE -MIA -MIB -MIC -MIE -VIA -VIB -VIC -VIE -LIA -LIB -LIC -LIE -EA -EB -EC -EE -EJ -EK -Ex for samples Tape and Reel available for ...

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