TS8388BMFSB/QNC3 Atmel Corporation, TS8388BMFSB/QNC3 Datasheet
TS8388BMFSB/QNC3
Related parts for TS8388BMFSB/QNC3
TS8388BMFSB/QNC3 Summary of contents
Page 1
Features • 8-bit Resolution • ADC Gain Adjust • 1.5 GHz Full Power Input Bandwidth (-3 dB) • 1 GSPS (min) Sampling Rate • SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc GSPS, ...
Page 2
Functional Description Block Diagram The following figure shows the simplified block diagram. Figure 1. Simplified Block Diagram MASTER/SLAVE TRACK & HOLD AMPLIFIER INB G=2 T/H G=1 CLK, CLKB CLOCK BUFFER DRRB DR, DRB Functional The TS8388BF ...
Page 3
Specifications Absolute Maximum Ratings Table 1. Absolute Maximum Ratings Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltage Analog input voltages Maximum difference between V and V IN ...
Page 4
Table 2. Recommended Operating Conditions (Continued) Parameter Symbol Differential analog input voltage V (Full Scale) V Clock input power level P Operating temperature range T Electrical Operating Digital outputs differentially terminated; Characteristics Tj ...
Page 5
Table 3. Electrical Specifications (Continued) Parameter Analog Inputs Full Scale Input Voltage range (differential mode) (0V common mode voltage) Full Scale Input Voltage range (single-ended input option) (See Application Notes) Analog input capacitance Input bias current Input Resistance Full Power ...
Page 6
Table 3. Electrical Specifications (Continued) Parameter Output levels (assuming V = 0V) PLUSD 75 differentially terminated: Logic “0” voltage Logic “1” voltage Output levels (assuming V = 0V) PLUSD 50 differentially terminated: Logic “0” voltage Logic “1” voltage Differential Output ...
Page 7
Table 3. Electrical Specifications (Continued) Parameter AC Performance Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), Binary output data format unless otherwise specified. Signal to Noise and Distortion ratio F = ...
Page 8
Table 3. Electrical Specifications (Continued) Parameter Minimum Clock pulse width (low) Aperture delay Aperture uncertainty Data output delay Output rise/fall time for DATA (20% – 80%) Output rise/fall time for DATA READY (20% – 80%) Data ready output delay Data ...
Page 9
Timing Diagrams Figure 2. TS8388BF Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at LOW Level (VIN, VINB) X N-1 (CLK, CLKB) 1360 ps DIGITAL 1000 ps OUTPUTS TDR = 1320 ps Data Ready (DR, DRB) DRRB ...
Page 10
Explanation of Test Levels Table 4. Explanation of Test Levels Num Notes: Functions Description Table 5. Functions Description Name Function V Positive power supply CC V Analog negative power supply EE V Digital positive power supply PLUSD GND Ground V ...
Page 11
Digital Output NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity volt- age errors. Coding Table 6. Digital Output Coding Differential Analog Input Voltage Level > +251 mV > Positive full scale + 1/2 ...
Page 12
Package Description Pin Description Table 7. TS8388BF Pin Description Symbol Pin number GND 5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51, 52, 53, 58 16, 17, 18, 68 PLUSD V 26, 29, ...
Page 13
TS8388BF Pinout Figure 4. TS8388BF Pinout VPLUSD D2B D1B D0B 25 GORB VCC 26 27 GND 28 GND 29 VCC 30 VEE ...
Page 14
Typical Characterization Results Static Linearity MSPS/F S Figure 5. Integral Non Linearity Note: Figure 6. Differential Non Linearity Note: TS8388BF MHz IN Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz; Positive peak: ...
Page 15
Effective Number Figure 7. Effective Number of Bits = Bits Versus Power Supplies Variation Figure 8. Effective Number of Bits = f (V Figure 9. Effective Number of Bits = f (V 2144A–BDC–04/02 EEA ...
Page 16
Typical FFT Results Figure 10 GSPS MHz S IN Figure 11 GSPS 495 MHz S IN Figure 12 GSPS 995 MHz (-3 dB Full ...
Page 17
Spurious Free Dynamic Range Versus Input Amplitude Figure 13. Sampling Frequency: F SINAD = 40 dB; SNR = 44 dB; THD = -46 dBc; SFDR = -47 dBc; Gray or Binary Output Coding Figure 14. Sampling Frequency: F SINAD = ...
Page 18
Dynamic GSPS Performance Clock duty cycle 50/50, Binary/Gray output coding, fully differential or single-ended analog and Versus Analog clock inputs. Input Frequency Figure 15. ENOB (dB 200 Figure ...
Page 19
Effective Number Analog Input Frequency Bits (ENOB) Clock duty cycle 50/50, Binary output coding Versus Sampling Frequency Figure 18. ENOB (dB) 8 FIN = FS/2 7 FIN = 500 MHz 200 SFDR ...
Page 20
TS8388BF ADC Performances Versus Junction Temperature Figure 20. Effective Number of Bits Versus Junction Temperature GSPS 500 MHz; Duty Cycle = 50 -40 -20 Figure 21. Signal ...
Page 21
Figure 23. Power Consumption Versus Junction Temperature GSPS 500 MHz; Duty Cycle = 50 -40 -20 Typical Full Power Input Bandwidth Figure 24. 1.5 GHz at -3 ...
Page 22
ADC Step Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps. Response Note: Figure 25. Test Pulse Digitized with 20 GHz DSO 0 0.5 1.0 Figure 26. Same Test Pulse Digitized with TS8388BF ...
Page 23
TS8388BF Main Features Timing Information Timing Value for Timing values as defined in Table 3 on page 4 are advanced data, issued from electric simula- TS8388BF tions and first characterizations results fitted with measurements. Timing values are given at CQFP68 ...
Page 24
Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values. In other terms : – – The external (on board) skew effect has NOT been ...
Page 25
Data Ready Output The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels Signal Restart (-0.8V). DRRB may also be Grounded allowed to float, for normal free running Data Ready output signal. The ...
Page 26
Differential Versus The TS8388BF can operate at full speed in either differential or single-ended configuration. Single-ended Analog This is explained by the fact the ADC uses a high input impedance differential preamplifier Input Operation stage, (preceeding the Sample and hold ...
Page 27
This is true so long as the inverted phase clock input pin is 50 terminated very closely to one of the neighboring shield ground pins, which constitutes the local Ground reference for the inphase clock input. Thus the TS8388BF differential ...
Page 28
Single-ended ECL In single-ended configuration enter on CLK (resp. CLKB) pin, with the inverted phase Clock Clock Input input pin CLKB (respectively CLK) connected to -1.3V through the 50 The inphase input amplitude is 1V peak to peak, centered on ...
Page 29
Three possible line driving and back-termination scenarios are proposed (assuming V 0V Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading Each output voltage varies between -1.02V and -1.35V (respectively ...
Page 30
Differential Output Loading Configurations (Levels for ECL Compatibility) Figure 32. Differential Output: 75 VPLUSD = 0V -0. DVEE Figure 33. Differential Output: 50 VPLUSD = 0V -0. DVEE ...
Page 31
Differential Output Loading Configurations (Levels for LVDS Compatibility) Figure 35. Differential Output: 75 VPLUSD = 2.4V 1. DVEE Figure 36. Differential Output: 50 VPLUSD = 2.4V 1. DVEE ...
Page 32
Out of Range Bit An Out of Range (OR, ORB) bit is provided that goes to logical high state when the input exceeds the positive full scale or falls below the negative full scale. When the analog input exceeds the ...
Page 33
ADC Gain Control The ADC gain is adjustable by the means of the pin 60 (input impedance with 2 pF). Pin 60 The gain adjust transfer function is given below. Figure 39. ADC Gain Control Pin 60 ...
Page 34
Equivalent Input/Output Schematics Figure 40. Equivalent Analog Input Circuit and ESD Protections VCC = +5V -0.8V GND = 0V -5.8V 50 E21V VEE 200 VIN Pad capacitance 340 fF 5.8V 0.8V E21G Note: The ESD protection equivalent capacitance is 150 ...
Page 35
Figure 42. Equivalent Data Output Buffer Circuit and ESD Protections E01V VEE OUT Pad capacitance 180 fF VEE = -5V Note: The ESD protection equivalent capacitance is 150 fF. Figure 43. ADC Gain Adjust Equivalent Analog Input Circuit and ESD ...
Page 36
Figure 44. GORB Equivalent Input Schematic and ESD Protections GORB: Gray or Binary Select Input; Floating or Tied to VCC -> Binary VEE GORB Pad capacitance 180 fF VEE = -5V Note: The ESD protection equivalent capacitance is 150 fF. ...
Page 37
TSEV8388BF: For complete specification, see separate TSEV8388B document. Device Evaluation Board General The TSEV8388BF Evaluation Board (EB board which has been designed in order to facil- itate the evaluation and the characterization of the TS8388BF device up to ...
Page 38
Nominal CQFP68 Although the power dissipation is low for this performance, the use of a heat sink is mandatory. Thermal Characteristics The user will find some advice on this topics below. Thermal Resistance The following table lists the converter thermal ...
Page 39
Thermal Resistance Typical value for Rthjc is given to 4.75 C/W. from Junction to Case: RTHJC CQFP68 Board Assembly Figure 47. CQFP68 Board Assembly with External Heatsink Printed circuit Aluminum heatsink Interface: Af-filled ...
Page 40
Enhanced CQFP68 Thermal Characteristics Enhanced CQFP68 The CQFP68 has been modified, in order to improve the thermal characteristics: • A CuW heatspreader has been added at the bottom of the package. • The die has been electrically isolated with the ...
Page 41
Definitions Definition of Terms (BER) Bit Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that dif- fers by more than (FPBW) Full Power Analog input frequency at which the fundamental ...
Page 42
Aperture Sample to sample variation in aperture delay. The voltage error due to jitter depends on the Uncertainty slew rate of the signal at the sampling point. (TS) Settling Time Time delay to achieve 0.2% accuracy at the converter ...
Page 43
Ordering Information Package Device Manufacturer prefix M: -55 C < Tc; Tj < 125 C Evaluation Board The evaluation board is delivered with an ADC and includes the heat sink. 2144A–BDC–04/02 TS 8388B M Device or family Temperature Range: V: ...
Page 44
Outline Figure 49. Package Dimension – 68-lead Ceramic Quad Flat Pack (CQFP) Dimensions TS8388BF 44 TOP VIEW 0.8 BCS 20.32 BSC 0.050 BCS Pin N 1 index 1.27 BSC CQFP 68 0.950 0.006 24.13 0.152 1.133 - 1.147 28.78 - ...
Page 45
Figure 50. Package Dimension – 68-lead Enhanced CQFP with Heatspreder 2144A–BDC–04/02 TOP VIEW 0.8 BCS 20.32 BSC 0.050 BCS Pin N 1 index 1.27 BSC CQFP 68 0.950 0.006 24.13 0.152 1.133 - 1.147 28.78 - 29.13 0.027 - 0.037 ...
Page 46
Datasheet Status Description Table 9. Datasheet Status Datasheet Status Objective specification Target specification Preliminary specification -site Preliminary specification -site Product specification Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one ...
Page 47
... Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...