74LV374N,112 NXP Semiconductors, 74LV374N,112 Datasheet

IC OCTAL D F-F POS-EDGE 20-DIP

74LV374N,112

Manufacturer Part Number
74LV374N,112
Description
IC OCTAL D F-F POS-EDGE 20-DIP
Manufacturer
NXP Semiconductors
Series
74LVr
Type
D-Type Busr
Datasheet

Specifications of 74LV374N,112

Output Type
Tri-State Non Inverted
Package / Case
20-DIP (0.300", 7.62mm)
Function
Standard
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
20MHz
Delay Time - Propagation
24ns
Trigger Type
Positive Edge
Current - Output High, Low
12mA, 12mA
Voltage - Supply
1 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Through Hole
Number Of Circuits
1
Logic Family
LV
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
14 ns at 3.3 V
High Level Output Current
- 16 mA
Low Level Output Current
16 mA
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
1 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2960-5
935063260112
1. General description
2. Features
3. Ordering information
Table 1.
Type number Package
74LV374
74LV374
74LV374
74LV374
N
D
DB
PW
Ordering information
Temperature range
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74LV374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop
and 3-state outputs for bus-oriented applications. A clock input (CP) and an output enable
input (OE) are common to all flip-flops. The 74LV374 is a low-voltage Si-gate CMOS
device and is pin and function compatible with 74HC374 and 74HCT374.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW to HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
I
I
I
I
I
I
I
I
I
74LV374
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 02 — 14 May 2009
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
Typical output ground bounce < 0.8 V at V
Typical HIGH-level output voltage (V
T
ESD protection:
Common 3-state output enable input
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
N
N
amb
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
= 25 C
Name
DIP20
SO20
SSOP20
TSSOP20 plastic thin shrink small outline package; 20 leads;
Description
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
plastic shrink small outline package; 20 leads;
body width 5.3 mm
body width 4.4 mm
CC
OH
) undershoot: > 2 V at V
= 2.7 V and V
CC
= 3.3 V and T
CC
= 3.6 V
amb
= 25 C
CC
Product data sheet
= 3.3 V and
Version
SOT146-1
SOT339-1
SOT360-1

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74LV374N,112 Summary of contents

Page 1

Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 02 — 14 May 2009 1. General description The 74LV374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) ...

Page 2

... NXP Semiconductors 4. Functional diagram Fig 1. Logic symbol Fig 3. Functional diagram 74LV374_2 Product data sheet Octal D-type flip-flop; positive edge-trigger; 3-state mna891 Fig FF1 D3 3-STATE OUTPUTS FF8 Rev. 02 — 14 May 2009 74LV374 mna196 IEC logic symbol mna892 © NXP B.V. 2009. All rights reserved. ...

Page 3

... NXP Semiconductors FF1 FF2 Fig 4. Logic diagram 5. Pinning information 5.1 Pinning 74LV374 GND 001aak107 Fig 5. Pin configuration DIP20, SO20 5.2 Pin description Table 2. Pin description Symbol Pin 12, 15, 16 13, 14, 17, 18 GND 74LV374_2 Product data sheet Octal D-type flip-flop; positive edge-trigger; 3-state ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating mode Input OE Load and read register L L Load register and disable H outputs H [ HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition ...

Page 5

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter [1] V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate [1] The static characteristics are guaranteed from ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I OFF-state output current OZ I supply current CC I additional supply current CC C input capacitance I [1] Typical values are measured ...

Page 7

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t disable time OE to Qn; dis pulse width CP, HIGH or LOW; see set-up time Dn to CP; see hold time Dn to CP; see maximum see max frequency power dissipation ...

Page 8

... NXP Semiconductors 11. Waveforms CP input Qn output Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 7. The clock (CP) to output (Qn) propagation delays, the clock (CP) pulse width and the maximum clock pulse frequency OE input output ...

Page 9

... NXP Semiconductors CP input Dn input Qn output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical output voltage levels that occur with the output load Fig 9. The data set-up and hold times for the Dn input to the CP input Table 8 ...

Page 10

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 10. Test circuit for measuring switching times Table 9. Test data ...

Page 11

... NXP Semiconductors 12. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 13. Package outline SOT339-1 (SSOP20) ...

Page 14

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 15

... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Quick reference data removed • Added type number 74LV374PW (TSSOP20 package) ...

Page 16

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 17

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Revision history ...

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