DA28F320S5-120 Intel, DA28F320S5-120 Datasheet
DA28F320S5-120
Related parts for DA28F320S5-120
DA28F320S5-120 Summary of contents
Page 1
... These alternatives give designers ultimate control of their code security needs. This family of products is manufactured on Intel’s 0.4 m ETOX™ V process technology. It comes in the industry-standard 56-lead SSOP. In addition, the 16-Mb device is available in the industry-standard 56-lead TSOP package. ...
Page 2
... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
Page 3
... Query Structure Output ..................... 16 4.2.2 Query Structure Overview ................. 18 4.2.3 Block Status Register ........................ 19 4.2.4 CFI Query Identification String........... 20 4.2.5 System Interface Information............. 21 4.2.6 Device Geometry Definition ............... 22 4.2.7 Intel-Specific Extended Query Table . 23 4.3 Read Identifier Codes Command ............. 24 4.4 Read Status Register Command.............. 24 4.5 Clear Status Register Command.............. 25 4.6 Block Erase Command ............................ 25 4.7 Full Chip Erase Command ....................... 25 ...
Page 4
REVISION HISTORY Number -001 Original version -002 Added commercial temperature information throughout the document. Updated address in Figure 5. Added descriptive information for CFI query to Section 4.2.5, System Interface Information Updated addresses and added descriptive information in ...
Page 5
... Finally, Section 7.0 provides ordering and reference information. 1.1 New Features The Word-Wide FlashFile memory family maintains basic compatibility with Intel’s 28F016SA and 28F016SV. Key enhancements include: Common Flash Interface (CFI) Support Scaleable Command Set (SCS) Support S5 Technology Enhanced Suspend Capabilities They share a compatible status register, basic software commands, and pinout ...
Page 6
Individual block locking uses a combination of block lock-bits to lock and unlock blocks. Block lock-bits gate block erase, full chip erase, program and write to buffer operations. Lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits ...
Page 7
Table 1. Pin Descriptions Sym Type A –A INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally 0 21 latched during a write cycle x16 mode not used; input buffer is off. 0 ...
Page 8
...
Page 9
...
Page 10
This code is copied to and executed from system RAM during flash memory updates. successful completion, reads are again possible via the Read Array command. Block erase suspend allows system ...
Page 11
... RESET# signal that resets the system CPU. 3.5 Read Query Operation The read query operation outputs block status, Common Flash Interface (CFI) ID string, system interface, device geometry, and Intel-specific extended query information. 3.6 Read Identifier Codes Operation The read-identifier codes operation outputs the ...
Page 12
A[ ]: 16-Mbit 20 32-Mbit 21-1 Word (Subsequent Blocks) Address 0FFFF Block 1 Reserved for Future Implementation 08004 08003 Block 1 Lock Configuration 08002 Reserved for Future Implementation 08000 07FFF Block 0 Reserved for Future Implementation ...
Page 13
Table 2. Bus Operations Mode Notes RP Read 1 Output Disable Standby Reset/Power Down Mode Read Identifier ...
Page 14
Table 3. Word-Wide FlashFile™ Memory Command Set Definitions Command Scaleable Bus or Basic Cycles Command Req'd Set (14) Read Array SCS/BCS 1 Read Identifier Codes SCS/BCS Read Query SCS Read Status Register SCS/BCS 2 Clear Status Register SCS/BCS ...
Page 15
... Commands other than those shown above are reserved for future use and should not be used. 14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set. ...
Page 16
Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for ...
Page 17
Table 4. Summary of Query Structure Output as a Function of Device and Mode Device Type/Mode Word Addressing Location x16 device/ 10h x16 mode 11h 12h x16 device/ N/A (1) x8 mode NOTE: 1. The system must drive the lowest ...
Page 18
... Refer to Section 4.2.1 and Table 4 for the detailed definition of offset address as a function of device word width and mode The beginning location of a Block Address (i.e., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table. 18 (1) ...
Page 19
BLOCK STATUS REGISTER The block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Table 7. Block Status Register Offset Length (bytes) (1) (BA+2)h ...
Page 20
CFI QUERY IDENTIFICATION STRING The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which vendor- specified command set(s) is (are) supported. Table 8. ...
Page 21
SYSTEM INTERFACE INFORMATION The following device information can be useful in optimizing system interface software. Table 9. System Interface Information Offset Length (bytes) 1Bh 01h V Logic Supply Minimum Program/Erase Voltage CC bits 7–4 BCD volts bits 3–0 BCD ...
Page 22
DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. Table 10. Device Geometry Definition Offset Length Description (bytes) 27h 01h Device Size = Number of Bytes 28h 02h Flash Device ...
Page 23
... INTEL-SPECIFIC EXTENDED QUERY TABLE Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. Table 11. Primary-Vendor Specific Extended Query Offset (1) Length (bytes) (P)h 03h Primary Extended Query Table Unique ASCII String “PRI“ ...
Page 24
Table 11. Primary-Vendor Specific Extended Query (Continued) Offset Length (bytes) (P+C)h 01h V Logic Supply Optimum Program/Erase voltage CC (highest performance) bits 7–4 bits 3–0 (P+D)h 01h V [Programming] Supply Optimum Program/Erase PP voltage bits 7–4 bits 3–0 ...
Page 25
Following a program, block erase, set block lock-bit, or clear block lock-bits command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O pins DQ and DQ are invalid. When the 0-6 8-15 ...
Page 26
This two-step command sequence of setup followed by execution ensures that block contents are not accidentally erased. An invalid Full Chip Erase command sequence will result in both status register bits SR.4 and SR.5 being set to 1. ...
Page 27
status register bits PP PPLK SR.4 and SR.3 will be set to “1.” Successful byte/word programming requires corresponding block lock-bit be cleared byte/word program is attempted when corresponding block lock-bit is set and ...
Page 28
The only other valid commands while programming is suspended are Read Status Register and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. Status register bits SR.2 and SR.7 will ...
Page 29
Table 13. Write Protection Alternatives Block Operation Lock- WP# Bit Program and Block Erase Full Chip Erase 0 Set or Clear ...
Page 30
Table 15. Status Register Definition WSMS ESS ECLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block erase suspended 0 = Block erase in ...
Page 31
Start Set Time-Out Issue Write Command No E8H, Block Address Read Extended Status Register 0 Write XSR.7 = Buffer Time-Out? 1 Write Word or Byte Count, Block Address Write Buffer Data, Start Address Yes Check X = ...
Page 32
Start Write 40H, Address Write Data and Address Read Status Register No Suspend 0 SR.7 = Byte/Word Program 1 Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 ...
Page 33
Start Write B0H Read Status Register 0 SR SR.2 = Programming Completed 1 Write FFH Read Data Array No Done Reading Yes Write D0H Write FFH Programming Resumed Read Array Data Figure 8. Program Suspend/Resume Flowchart ADVANCED ...
Page 34
Start Device Supports Queuing Yes Set Time-Out Issue Block Queue Erase Command 28H, Block Address No Read Extended Status Register Is Queue Erase Block 0=No Available? Time-Out? XSR.7= 1=Yes Another Block Erase? Yes Yes Issue Erase Command 28H ...
Page 35
Start Write B0H Read Status Register 0 SR SR.6 = Block Erase Completed 1 Read Program Read or Program? Read Array Program No Data Loop Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data ...
Page 36
Start Write 60H, Block/Device Address Write 01H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage ...
Page 37
Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range Error 0 1 SR. ...
Page 38
... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control Intel provides three control inputs to accommodate multiple memory connections ( OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation; b. Data bus contention avoidance. To use these control inputs efficiently, an address decoder should enable CEx# while OE# should be connected to all memory devices and the system’ ...
Page 39
... Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design * WARNING: Stressing the device beyond the “Absolute Maximum Ratings” ...
Page 40
Capacitance T = +25 ° MHz A Symbol Parameter C Input Capacitance IN C Output Capacitance OUT NOTE: 1. Sampled, not 100% tested. 6.4 DC Characteristics – ...
Page 41
DC Characteristics (Continued – +85 C (Extended) and T A Sym Parameter I V Programming and Set CCW CC Lock-Bit Current I V Block Erase or Clear Block CCE CC Lock-Bits Current I ...
Page 42
DC Characteristics (Continued – +85 C (Extended) and T A Sym Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage ...
Page 43
Input 1.5 0.0 AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to ...
Page 44
AC Characteristics—Read-Only Operations – +85 C (Extended) and T A Versions (4) (All units in ns unless otherwise noted) # Sym Parameter R1 t Read/Write Cycle Time AVAV R2 t Address ...
Page 45
Device Standby Address Selection V IH ADDRESSES ( ( OE# ( WE# ( DATA (D/Q) High Z (DQ0-DQ15 ...
Page 46
AC Characteristics—Write Operations – +85 C (Extended) and T A Versions (6) # Sym RP# High Recovery to WE# (CE ) PHWL PHEL ...
Page 47
ADDRESSES [ (WE#) [E(W OE# [ WE# (CE #) [W(E ...
Page 48
V IH STS ( RP# ( CC1 Figure 18. AC Waveform for Reset Operation Table 18. Reset AC Specifications # Sym Parameter P1 t ...
Page 49
Erase, Write, and Lock-Bit Configuration Performance Version # Sym W16 Byte/word program time (using write buffer) W16 t Per byte program time (without write buffer) WHQV1 t EHQV1 W16 t Per word program time (without write buffer) WHQV1 t ...
Page 50
... ADDITIONAL INFORMATION 7.1 Device Nomenclature and Ordering Information Package DT = Extended Temp. 56-Lead SSOP TE = Extended Temp. 56-Lead TSOP Product Line Designator for all Intel Flash products Device Density 160 = 16 Mbit 320 = 32 Mbit Order Code by Density TE28F160S5-70 ...
Page 51
... CFI - Common Flash Interface Reference Code Sales Office NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. ...