ADN8810 Analog Devices, ADN8810 Datasheet
ADN8810
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ADN8810 Summary of contents
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... The 3-bit address allows up to eight devices to be independently controlled while attached to the same SPI bus. The ADN8810 is guaranteed with ± 4 LSB INL and ± 0.75 LSB DNL. Noise and digital feedthrough are kept low to ensure low jitter operation for laser diode applications. Full-scale and scaled output currents are given in Equations 1 and 2, respectively ...
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... REVISION HISTORY Revision 0: Initial Version Serial Data Interface................................................................... 11 Standby and Reset Modes ......................................................... 12 Power Dissipation ...................................................................... 12 Using Multiple ADN8810s for Additional Output Current . 12 Adding Dither to the Output Current ..................................... 12 Driving Common-Anode Laser Diodes ................................. 13 PC Board Layout Recommendations ...................................... 13 Suggested Pad Layout for CP-24 Package ............................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide ...
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... PVDD AVDD PVDD V DVDD = 5 DVDD = 5 DVDD = 3 DVDD = DVDD = 3 DVDD = 5 V Rev Page ADN8810 Min Typ Max Unit 12 Bit ± 4 LSB ± 0.75 LSB 4 8 LSB 15 ppm/°C 1 %FS 3.9 4.096 4 µA 2 ...
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... ADN8810 Parameter 2 INTERFACE TIMING Clock Frequency RESET Pulsewidth NOTES 1 With respect to AVSS. 2 See Timing Characteristics for timing specifications Ω SN Symbol Condition f CLK t 11 Rev Page Min Typ Max Unit 12.5 MHz 40 ns ...
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... ADDRESS BIT A3 MUST BE LOGIC LOW )/ D11 Figure 2. Timing Diagram Rev Page Min Typ Max 12 D10 ADN8810 Unit MHz ...
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... ADN8810 ABSOLUTE MAXIMUM RATINGS Table 3. ADN8810 Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range CP Package Lead Temperature Range (Soldering 10 sec) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
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... Connect to Analog Ground or Most Negative Potential in Dual-Supply Applications No Connection Connect to Digital Ground or Most Negative Potential in Dual-Supply Applications Serial Data Input Serial Clock Input Chip Select; Active Low Asynchronous Reset to Return DAC Output to Code Zero; Active Low Power Supply for Digital Interface Digital Ground Rev Page ADN8810 ...
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... INL, DNL, and gain error specifications. Output Current Change vs. Output Voltage Change This is a measure of the ADN8810 output impedance and is similar to a load regulation spec in voltage references. For a given code, the output current changes slightly as output voltage increases ...
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... Rev Page – TEMPERATURE (°C) Figure 8. ∆ DNL vs. Temperature = 1.6Ω S – TEMPERATURE (°C) Figure 9. Full-Scale Output vs. Temperature R = 20Ω S – TEMPERATURE (°C) Figure 10. Full-Scale Output vs. Temperature ADN8810 ...
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... ADN8810 0.50 CODE = x000 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 –40 –15 10 TEMPERATURE (°C) Figure 11. PVDD Supply Current vs. Temperature 12 CODE = x000 –40 –15 10 TEMPERATURE (°C) Figure 12. DVDD Supply Current vs. Temperature 1.5 CODE = x000 1.4 1.3 1.2 1.1 1.0 –40 –15 10 TEMPERATURE (°C) Figure 13. AVDD Supply Current vs. Temperature Rev ...
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... CS loads the shift register byte into the ADN8810. If more than 16 bits of data are clocked into the shift register before CS goes high, bits will be pushed out of the register in first-in first- out (FIFO) fashion ...
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... ADN8810 pins ADDR2, ADDR1, and ADDR0 to VDD sets this address. Example 2: This input sets the device with an address of 000 to a current equal to half of the full-scale output. Example 3: The ADN8810 with an address of 100 is set to full- scale output. STANDBY AND RESET MODES Applying a logic low to the SB pin deactivates the ADN8810 and puts the output into a high impedance state ...
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... The maximum output current of this configuration is limited by the compliance voltage at the IOUT pin of the ADN8810. The voltage at IOUT cannot exceed 1 V below PVDD, in this case 4 V. The IOUT voltage is equal to the voltage drop across R the gate-to-source voltage of the external FET ...
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... SUGGESTED PAD LAYOUT FOR CP-24 PACKAGE shows the dimensions for the PC board pad layout for the GND ADN8810. The package × 4 mm, 24-lead LFCSP. The metallic slug underneath the package should be soldered to a copper pad connected to AVSS, the lowest supply voltage to the ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range ADN8810ACP –40°C to +85°C ADN8810ACP- REEL7 –40°C to +85°C ADN8810-EVAL 4.00 BSC SQ 0.60 MAX 0.50 BSC TOP 3.75 VIEW BSC SQ 0.50 0.40 0.30 0.80 MAX 12° MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.30 0.08 0.20 REF 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 Figure 26 ...
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... ADN8810 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03195-0-1/04(0) Rev Page ...