74HC574DTR2G ON Semiconductor, 74HC574DTR2G Datasheet

IC FLIP FLOP OCT 3ST D 20-TSSOP

74HC574DTR2G

Manufacturer Part Number
74HC574DTR2G
Description
IC FLIP FLOP OCT 3ST D 20-TSSOP
Manufacturer
ON Semiconductor
Series
74HCr
Type
D-Type Busr
Datasheet

Specifications of 74HC574DTR2G

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
28MHz
Delay Time - Propagation
34ns
Trigger Type
Positive Edge
Current - Output High, Low
7.8mA, 7.8mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74HC574DTR2GOSTR
74HC574
Octal 3−State Noninverting
D Flip−Flop
High−Performance Silicon−Gate CMOS
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
rising edge of the Clock. The Output Enable input does not affect the
states of the flip−flops but when Output Enable is high, all device
outputs are forced to the high−impedance state. Thus, data may be
stored even when the outputs are not enabled.
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
Features
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
The 74HC574 is identical in pinout to the LS574. The device inputs
Data meeting the set−up time is clocked to the outputs with the
The HC574 is identical in function to the HC374A but has the
No. 7A
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
In Compliance with the Requirements Defined by JEDEC Standard
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
This is a Pb−Free Device
1
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
20
(Note: Microdot may be in either location)
1
ORDERING INFORMATION
HC574 = Device Code
A
L
Y
W
G
http://onsemi.com
CASE 948E
DT SUFFIX
TSSOP−20
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
20
1
DIAGRAMS
MARKING
ALYW G
74HC574/D
574
HC
G

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74HC574DTR2G Summary of contents

Page 1

Octal 3−State Noninverting D Flip−Flop High−Performance Silicon−Gate CMOS The 74HC574 is identical in pinout to the LS574. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. Data meeting the set−up ...

Page 2

OUTPUT ENABLE GND 10 ...

Page 3

... Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level. ORDERING INFORMATION Device 74HC574DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...

Page 4

... Maximum Low−Level Output OL Voltage I Maximum Input Leakage in Current I Maximum Three−State OZ Leakage Current I Maximum Quiescent Supply CC Current (per Package) 7. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D). (Voltages Referenced to GND (V) Test Conditions – 0.1 V 2.0 out CC 3 out 4 ...

Page 5

... C Maximum Three−State Output Capacitance, Output in High−Impedance out State 8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). C Power Dissipation Capacitance (Per Enabled Output)* PD *Used to determine the no−load dynamic power consumption: P Semiconductor High− ...

Page 6

CLOCK 50% 10 1/f max t t PLH PHL 90% Q 50% 10 TLH THL Figure 3. VALID DATA 50 CLOCK 50% Figure 5. TEST POINT CONNECT ...

Page 7

... −V− 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE Í Í Í Í ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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