IR3522 International Rectifier, IR3522 Datasheet
IR3522
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IR3522 Summary of contents
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... DESCRIPTION The IR3522 Control IC combined with IR3506 xPHASE3 power solution. The IR3522 provides control functions for both the VTT (single phase) and VDDR (multiphase) power rails which can interfaces with any number of IR3506 ICs each driving and monitoring a single phase to power any number of DDR3 DIMMs. The xPHASE3 supply that is smaller, more flexible, and easier to design while providing higher efficiency than conventional approaches ...
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... SDA (Serial Data bidirectional signal that is an input and open drain output for 2 both master (I C controller) and slave (IR3522). SDA requires a pull resistor to a bias voltage and should not be floated. Input to provide bias to the Power Good output transistor directly from the converter input voltage ...
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... The Power Good function also monitors output voltages and this pin will drive low if any of the voltage planes are outside of the specified limits. Connect external pull-up. SCL (Serial Clock open drain output of the I This pin requires an external bias voltage and should not be floated. IR3522 2 C controller and input to IR3522. V3.01 ...
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... V(VCCL) + 1.1 V -0.3V 8V -0.3V 8V -0.3V n/a n/a 8V -0.3V 8V -0.3V 8V -0.3V 8V -0.3V 8V -0.3V 8V -0.3V VCCL + 0.3V -0.3V 8V -0.3V IR3522 I I SOURCE SINK 1mA 10mA 1mA 1mA 1mA 1mA 5mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 25mA 10mA 1mA 1mA 5mA 25mA 5mA 1mA 5mA 1mA 5mA 1mA 5mA 1mA 5mA ...
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... V ≤ V(VOSEN1+) - V(VOSEN1-) ≤ 1.6125 V, 385mV ≤ V(VOSEN2+) - V(VOSEN2-) ≤ 1.021 V 1.025 V ≤ V(VOSEN1+) - V(VOSEN1-) ≤ 1.6125 V, 385mV ≤ V(VOSEN2+) - V(VOSEN2-) ≤ 1.021 V, All VID Codes V(VCCL) =7V V(VCCL) – V(VOUTx) IR3522 ≤ 0.1uF OSC SS/DEL1 MIN TYP MAX UNIT 1 ...
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... V(EAOUTx)=V(VCCL) to PGOOD = low. With FB2 grounded, V(VOUT1)/2 when EAOUT2 drives high Includes I(OCSET1) and I(OCSET2) VOUT1 referenced to VREF1 VOUT2 referenced to VOUT1/2 VOUT1 referenced to VREF1 VOUT2 referenced to VOUT1/2 I(PGOOD) = 3mA V( PGOOD ) = 5.5V I( PGOOD )=2mA, V(PGOOD) = 300mV I(PGBIAS) = 100uA IR3522 MIN TYP MAX UNIT 1 2.9 3 ...
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... V(VOUTx) < [V(VOSENx+) – V(LGND Compare to V(VCCL) V(VOUTx) = 100mV Pull-up to 3.3 V typical 0V ≤ V(x) ≤ 3.5V Noise Pulse < 100ns will not register an ENABLE state change. Note 1 1V ≤ V(OCSETx) ≤ 3.3V ROSC value, Note 1 ROSC value, Note 1 IR3522 MIN TYP MAX UNIT 230 260 300 mV -20 0 ...
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... CURRENT AMPLIFIER IROSC 0.6V SOURCE + GENERATOR - REMOTE SENSE AMPLIFIER + - Figure 2A - Output 1 System Set Point Test Circuit ERROR AMPLIFIER 2 + VREF_TRACK - REMOTE SENSE AMPLIFIER Figure 2B - Output 2 System Set Point Test Circuit IR3522 MIN TYP MAX 3 4.20 4.43 4.7 3.8 3.99 4.3 0.36 0.42 0.46 EAOUT1 FB1 VREF1 OC SET1 ROCSET1 IOCSET1 RVREF1 CVREF1 ...
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... The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. . IR3522 CONTROL IC CLOCK GENERATOR CLKOUT PHSOUT ...
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... An additional advantage of this architecture is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 5 depicts PWM operating waveforms under various conditions. Page 10 Figure 4 Four Phase Oscillator Waveforms IR3522 V3.01 ...
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... Current Sense Amp CSOUT IR3522 DUTY CYCLE DECREASE DUE TO LOAD STEADY-STATE DECREASE (BODY BRAKING) OR FAULT OPERATION (VCC UV, OCP, VID FAULT the two time constants match, the voltage ...
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... PWM starting point decreasing its duty cycle and output current. The current share amplifier is internally compensated so that the crossover frequency, of the current share loop, is much slower than that of the voltage loop and the two loops do not interact. www.DataSheet4U.com Page 12 IR3522 V3.01 ...
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... IR3522 THEORY OF OPERATION Block Diagram The Block diagram of the IR3522 is shown in Figure 7. The following discussions are applicable to either output plane unless otherwise specified. ENABLE VCCL LGND IIN1 OCSET1 IIN2 OCSET2 EAOUT2 FB2 www.DataSheet4U.com VOUT2 VOSEN2+ VOSEN2- DETECT PULSE1 SS_DI SCHARGED VREF BUFFER ...
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... Addresses and data are serially transmitted in 8-bit words. The first data bit of the SVID data word represents the PSI_L bit and will be ignored by the IR3522 therefore this system will never enter a power-saving mode. The remaining data bits SVID[6:0] select the desired VOUTx regulation voltage as defined in Table 2 or Table 3 depending address chosen ...
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... VID OFF, no change in VREF or VTT (VIDX pin controlled codes are in Gray) IR3522 VOUT2 0.80625 0.8 0.79375 0.7875 0.78125 0.775 0.76875 0.7625 0.75625 0.75 0.74375 0.7375 0.73125 0.725 0.71875 0.7125 0.70625 ...
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... VID OFF Table 3 – Vtt Margining (Default in Gray) Pre-ENABLE VREF1 Codes VID1 VID0 Table 4 – Pre-Enable VDDR program Codes IR3522 % Change from VOUT1 63.16 62.35 61.52 60.70 59.87 59.06 58.23 57.40 56.59 55.78 54.94 54.12 53.28 52.46 51.64 50.82 50 49.16 48.31 47.46 46.61 45.78 44.93 44.08 43.25 42.42 41.58 40.74 39.90 39.08 38.21 37.44 VID OFF VDDR 1.05 1 ...
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... Control Fault (VCCL) ENABLE CLEARED Latch Recycle EN or Cycle VID_OFF through SVID Both Yes No Yes Yes Delay PHSOUT Counter Pulses Yes, Table 5 – IR3522 Fault protocol OC Over Disable VID_OFF Voltage SVID SS Latch SS discharge below 0.22V No Yes No No 250ns No Blanking Time V3.01 ...
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... IR3522 will reply with an acknowledge ACK bit if the address is one of the two stored addresses otherwise the ACK bit will not be sent out. The SDA pin is pulled low by the IR3522 to generate the ACK bit. Table 1 has the list of addresses recognized by the IR3522. ...
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... Start-up Sequence The IR3522 is designed as a chipset with the IR3506 Phase IC to achieve output voltage tracking. VOUT2’s internal reference (VREF_TRACK) is generated by a divided-by-half internal resistor divider. This will ensure VOUT2 remains half the value of VOUT1 preventing possible damage to some DDR system’s microprocessors. In addition, a track-fault comparator is implemented to monitor both outputs which will further guarantee the outputs remain at least 1 ...
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... VREF1 VREF_TRACK 0.8V Tracks EAOUT1 EAOUT2 VOUT1 ON NORMAL VOUT2 ON THE FLY THE FLY MARGINING OPERATION MARGINING Figure 10 SVID Start-up Sequence Transitions IR3522 SVID OFF COMMAND SVID ON COMMAND SVID OFF COMMAND SVID ON COMMAND SVID programmed voltage 1.4V Soft Stop SVID OFF TRANSITION SVID ON TRANSITION V3.01 ...
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... ENABLE pin or VID_OFF command. VCCL Under Voltage Lockout (UVLO) The IR3522 monitors the VCCL supply voltage to determine if the amplitude is proper to adequately drive the top and bottom gates. As VCCL begins to rise during power up, the IC is allowed to power up when VCCL reaches 4.43 V (Typical) ...
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... Open Sense Fault Latch can only be reset by cycling the ENABLE pin or the VID_OFF command. Open Daisy Chain Protection The IR3522 checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and detects the feedback at PHSIN pin pulse comes back after 30 CLKOUT pulses, the pulse is restarted again. If the pulse fails to come back the second time, the Open Daisy Chain fault is registered, and SS/DEL to charge ...
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... All the output components are selected using one output but suitable for both unless otherwise specified. Oscillator Resistor R osc R The only one oscillator of IR3522 generates square-wave pulses to synchronize the phase ICs. The switching frequency of the each phase converter equals the PHSOUT frequency, which is set by the external resistor R , use Figure 11 to determine the R ROSC multiplied by the phase number ...
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... (1) ( − − SVID (3) − (4) VDAC VDAC is used to compensate VDAC circuit and is VDAC (5) (6) (7) is the inductor DCR the required over current LIMIT ] ∗ (9) CS OCSET (10) IR3522 as defined in is the ratio P V3.01 ...
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... Rcp = Ccp Cfb = Ccp = Rfb wp Page 25 and Resistor Pre-select the capacitor Rfb 1 1 ⋅ ⋅ Rfb ⋅ Rcp 1 1 ⋅ Cfb IR3522 and capacitor CS and calculate (11) (12) (13) (14) (15) (16) V3.01 ...
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... Rc ⋅ C ⋅ ⋅ t − t ⋅ ⋅ Figure 12 Voltage Loop Compensation Network (17) (18) (19) (20) 2 ⋅ Rst ) (21) (22) (23) (24) (25) (26) (27 ⋅ − b ⋅ − (28 ⋅ t ⋅ (29 IR3522 V3.01 ...
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... Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes. • Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation • components. www.DataSheet4U.com Page 27 IR3522 V3.01 ...
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... A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. • No pcb traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so can cause the IC to rise up from the pcb resulting in poor solder joints to the IC leads. www.DataSheet4U.com Page 28 IR3522 V3.01 ...
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... Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. • The single via in the land pad should be tented or plugged from bottom boardside with solder resist. www.DataSheet4U.com Page 29 IR3522 V3.01 ...
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... The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. www.DataSheet4U.com Page 30 IR3522 V3.01 ...
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... PACKAGE INFORMATION www.DataSheet4U.com Page 31 32L MLPQ ( Body) θ =24.4 JA IR3522 o o C/W, θ =0.86 C/W JC V3.01 ...
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... IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Page 32 Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. Visit us at www.irf.com for sales contact information. IR3522 TAC Fax: (310) 252-7903 www.irf.com V3.01 ...