IR3Y48M Sharp Electrionic Components, IR3Y48M Datasheet
IR3Y48M
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IR3Y48M Summary of contents
Page 1
... IR3Y48M DESCRIPTION The IR3Y48M is a CMOS single-chip signal processing IC for CCD area sensors which includes correlated double sampling circuit (CDS), clamp circuit, automatic gain control amplifier (AGC), reference voltage generator, black level detection circuit, 20 MHz 10-bit analog-to-digital converter (ADC), timing circuit for internally required pulses, and serial interface for internal circuits ...
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... OBP CCDCLP MONOUT 16 AGC AGC ROUGH FINE + 6 dB/STEP 0.094 dB/STEP ( dB dB) DAC OBP SERIAL REGISTER ADCLP CSN SCK SDATA OP RESETN 2 IR3Y48M BANDGAP V REF COM 10-BIT DO ADC DD1 6,7 AV DD2 34 AV ...
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... GND V DD ◊ GND V DD ◊ GND V DD ◊ GND 3 IR3Y48M DESCRIPTION No connection. Supply of 2.7 to 3.6 V analog power. No connection. ADC internal negative reference voltage. (Connect to AV via 0.1 µF.) SS ADC internal positive reference voltage. (Connect to AV via 0.1 µF.) SS Supply of 2.7 to 3.6 V analog power. ...
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... OP I ◊ Internal gate EQUIVALENT CIRCUIT V 18 ◊ GND V GND V GND 4 IR3Y48M DESCRIPTION No connection. Internal analog circuit bias input. DD (Connect to AV via 4.7 k$.) SS Supply of 2.7 to 3.6 V analog power. An analog grounding pin. No connection. ADC sampling clock input. Reference sampling pulse input. Data sampling pulse input. ...
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... EQUIVALENT CIRCUIT V DD GND V DD GND on PCB even they are not connected electrically in the chip IR3Y48M DESCRIPTION ADC digital output (LSB). (Capable of High-Z) ADC digital output. (Capable of High-Z) ADC digital output. (Capable of High-Z) ADC digital output. (Capable of High-Z) ADC digital output. ...
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... FUNCTIONAL DESCRIPTION Outline The configuration of IR3Y48M is described below. SHR SHD Clamp REFIN CDS CCDIN CCD ADIN Timing ADCK Generator BLK OBP CCDCLP ADCLP CCD OB ADCK BLK OBP CCDCLP DO -DO Data Output 0 9 MONOUT IR3Y48M + AGC Black Control Serial Register CSN SCK ...
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... C-coupling. Place the same capacitor between REFIN and AV Reference Clock (SHR) Data Clock (SHD) REFIN CDS CDS Output = V (CDS) CCDIN = V (DAT) – V (PREC) CDS Operation Reset Pulse V (PREC) SHR SHD SIG SIG MHz / SMAX SMIN 7 IR3Y48M . SS V (CDS) V (DAT) MAX. Level SHD ...
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... Normally clamp switch is turned on at black level calibration capacitance between CLPCAP and AV CCD ADCK CLPCAP CCDCLP REFIN, CCDIN CLPCAP Clamp Level ADIN ADIN DC Clamp Function 8 IR3Y48M period. Place 0.1 µF external . SS Clamp Timing CLPCAP Level ADCLP Timing Control To AGC or ...
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... OB control are done simultaneously) instead of OBP. AGC AGC Rough Fine + DAC Compare OBP Register (7-bit) ADCLP OBP ADCLP Black Level Calibration Optical Black Period Black Level Calibration Timing 9 IR3Y48M 10-bit ADC Effective Blanking Pixel Signal Resulting Black Calibration Level (Hold) ...
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... The gain is fixed to maximum gain when the code exceeds 382 (decimal). The gain of ADIN (which bypassing CDS dB. 1 step 0D 383D AGC Block Rough 6 dB/step ( dB) Total Gain = 0 to 35.91 dB Gain Control 10 IR3Y48M 0.094 dB Fine 0.094 dB/step ( dB) ...
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... A/D Converter Circuit IR3Y48M integrates 20 MHz 10-bit full pipeline A/D converter (ADC). A/D CONVERSION RANGE The analog input range of the ADC is determined by V circuit integrated in IR3Y48M. At ADC REF direct input (ADIN) mode (Mode (1) Register D 1), feed 1 Vp-p (full scale) signal based on clamp level as zero reference into ADIN input pin. ...
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... Black Cancel & Clamp ADIN Signal Processing (AGC Input) ADCLP pulse. The ADIN input range is from CLPCAP + 1 V (TYP.) (full scale). Full scale ADIN Signal Input Level If one of the above is set, IR3Y48M powers down. ("OR" logic) 12 IR3Y48M N CLPCAP + 1 V ADC ...
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... No signal level 0 MONOUT MON reference level = V COM POLARITY INVERSION Following timing pulse of IR3Y48M control can be inverted by register setting : q ADCK (A/D converter sampling pulse) w SHR, SHD (CDS sampling clock) e BLK, OBP, CCDCLP, ADCLP (Enable controls) POWER SAVE Power save mode is selectable for the sampling frequency below 15 MHz ...
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... Serial Interface Circuit The internal registers of IR3Y48M are controlled through 3-wire serial interface. The 16-bit length control data consists of 2-bit operation code, 4-bit address, and 10-bit data. The controller should set each bit synchronizing to SCK falling since IR3Y48M (receiver) acquire data at SCK rising edge ...
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... Registers IR3Y48M has 10-bit x 5 registers to control its operations. All registers are write only. The serial registers are written by serial interface. Register Map R/W ADDRESS REFERENCE NAME Mode ( Mode ( Gain ...
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... ADIN signal to AGC 1 X ADIN signal to ADC 0 20 MHz mode 1 15 MHz mode 0 Normal operation [ADC data output] 1 ADC output High-Z [or logic of STBYN] 0 Normal operation 1 Black level reset [or logic of RESETN] 0 Normal operation 1 Standby [or logic of STBYN] 16 IR3Y48M OPERATIONS NOTE Don't care ...
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... Normal operation as timing chart 0 1 S/H control polarity inversion 1 0 Enable control polarity inversion 1 1 Both of S/H and enable inversion 0 0 Monitor OFF 0 1 CDS signal to monitor 1 0 AGC output monitor 1 1 Output REFIN and CCDIN (for calibration) 17 IR3Y48M OPERATIONS NOTE ...
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... IR3Y48M TOTAL HEX GAIN (dB 0.000 1 1 0.094 2 2 0.188 3 3 0.281 4 4 0.375 3E 5.813 3F 5.906 40 6.000 41 6.094 80 12.000 C0 18.000 100 24.000 140 30 ...
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... IR3Y48M TOTAL HEX GAIN (dB 0.000 1 1 0.094 2 2 0.188 3 3 0.281 4 4 0.375 3E 5.813 3F 5.906 40 6.000 41 6.094 80 12.000 C0 18.000 FE 23.813 FF 23.906 100 23 ...
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... IR3Y48M HEX NOTE FORBIDDEN 124 7C 125 7D 126 7E 127 ...
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... X : Don't care CONTROLS Normal operation 1 V COM Connect C-coupled output to ADIN. The resistance 50 k$ between ADIN (14 pin) and CLPCAP (13 pin) stabilize the DC level at ADIN pin. 21 IR3Y48M OPERATIONS centered ADIN for AC coupling ...
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... DD AV – – –30 to +85 ˚C –40 to +125 ˚C MIN. TYP. MAX. before (or at 2.7 3.0 3.6 . 2.7 3 +25 ˚ MIN. TYP. MAX. UNIT 3 0.1 mA IR3Y48M NOTE 1 2 UNIT 3.0 V) NOTE 1 2 ...
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... If the black level settling specification (within 2 000 pixels) could be ignored, the maximum sampling frequency for 0.1 µF and 0.33 µF will extend according to the increment. PARAMETER MODE Available sampling frequency 23 IR3Y48M = 1 MHz, IN (Sampling frequency MHz) S MIN. TYP. MAX. UNIT NOTE 1 ...
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... MHz mode MHz DNL (At 15 MHz mode) SN SND V COM CCAL ST CAL ) is specified for code = 16 to 127 LSB. is not guaranteed for these codes. BKCAL 24 IR3Y48M MIN. TYP. MAX. UNIT NOTE –1.9 –0.9 0.1 dB 34.906 35.906 36.906 dB 0 0.094 0.188 dB –1.3 –0.3 0 ...
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... SUR t SUD SUE Active/High-Z DLD t High-Z/Active DLE t DL1 t DL2 25 IR3Y48M = –30 to +85 ˚C, C < 10 pF) OPR L MIN. TYP. MAX. UNIT NOTE 0.5 20 MHz –3 ...
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... ADCK ADC Input N Sampling Point Digital Output N – SUR SUD t CYC ADIN : ADC Direct Input DL1 N – – DL2 26 IR3Y48M t SUE 0.7AV DD 0.3AV 5.5 clk delay 0.7DV DD N – 0.3DV DD ...
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... ADCK by register setting. (The figure shown on the previous page is the default, the following is the inverted one.) Clock Waveform t H 0.7AV DD 0.3AV [When ADCK Inverted by Register DL1 N – – DL2 CYC 27 IR3Y48M 0.7AV DD 0.3AV 6.0 clk delay 0.7DV DD N – 0.3DV DD ...
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... –30 to +85 ˚C, measured as DC characteristics OPR SYMBOL CONDITIONS V IL1 V IH1 – LING IR3Y48M = –30 to +85 ˚C) SS OPR MIN. TYP. MAX. UNIT 10 MHz pcs 50%DV ...
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... Pixel Data Readout Sequence (1) : Conversion Start CCD (N – 1) (N) SHR SHD ADCK BLK DO - – – 7 Pixel Data Readout Sequence (2) : Conversion End Black Level Code N – – – – – – IR3Y48M ...
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... µ (TYP.) SIO CONTROL PULSE 0.1 µ TOP VIEW 0.1 µF 30 IR3Y48M 26 25 SHD 24 SAMPLING SHR 23 PULSE ADCK SS1 0.1 µ DD1 4.7 k$ AISET MONOUT 16 MONITOR 0.033 µF OBCAP 15 ADIN ...
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PACKAGE 48 QFP (QFP048-P-0707) PACKAGES FOR CCD AND CMOS DEVICES 0.5 TYP. 0.2 ±0. (1.0) (1.0) ±0.2 ±0.2 7.0 0.65 1.45 ±0.2 9.0 ±0.3 31 (Unit : mm) 0.15 ±0.05 0.1 ±0.1 ...