RM5261-200-QI PMC-Sierra Inc, RM5261-200-QI Datasheet
RM5261-200-QI
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RM5261-200-QI Summary of contents
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... RM5261™ Microprocessor with 64-Bit Proprietary and Confidential Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet RM5261 System Bus Data Sheet Issue 1, March 2001 Released ...
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... Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Released 2 ...
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... Revision History Issue No. Issue Date 1 March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet ECN Number Originator Details of Change 3828 T. Chapman Applied PMC-Sierra template to existing MPD (QED) FrameMaker document ...
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... Interrupt Mask, are in an italic-bold typeface. •All instruction names, such as MFHI, are in san serif typeface. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Released 4 ...
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... Handshake Signals ......................................................................................................22 3.25 Non-overlapping System Interface ...............................................................................22 3.26 Enhanced Write Modes ................................................................................................23 3.27 External Requests ........................................................................................................24 3.28 Interrupt Handling ........................................................................................................24 3.29 Standby Mode ..............................................................................................................24 3.30 JTAG Interface .............................................................................................................24 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Released 5 ...
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... Timing Diagrams ...................................................................................................................35 10.1 System Interface Timing ..............................................................................................35 11 Packaging Information ..........................................................................................................36 12 RM5261 208-pin PQFP Package Pinout ...............................................................................38 13 Ordering Information .............................................................................................................40 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Released 6 ...
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... Figure 7 Processor Block Read .................................................................................................23 Figure 8 Processor Block Write .................................................................................................23 Figure 9 Clock Timing ................................................................................................................35 Figure 10 Input Timing ...............................................................................................................35 Figure 11 Output Timing ............................................................................................................35 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Released 7 ...
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... Table 7 Interrupt Interface .........................................................................................................27 Table 8 JTAG Interface .............................................................................................................27 Table 9 Initialization Interface ....................................................................................................28 Table 10 Power Supply .............................................................................................................28 Table 11 DC Electrical Characteristics ......................................................................................31 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Released 8 ...
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... Standby reduced power mode with WAIT instruction • 2.5 V core with 3.3 V IOs • 208-pin PQFP package Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Released 9 ...
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... Register File Packer/Unpacker Floating-Point MultAdd, Add, Sub, Cvt, Div, Sqrt Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet DTag ITag DTLB ITLB Pad Buffer Address Buffer ...
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... The key elements of the RM5261 are briefly described below. 3.1 Superscalar Dispatch The RM5261 has an asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. Integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc ...
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... In addition to the integer pipeline, the RM5261 implements an extended 7-stage pipeline for floating-point operations. The RM5261 multiplies the input SysClock by 2, 2.5, 3, 3. produce the pipeline clock. Figure 3 shows the RM5261 integer pipeline. As illustrated in the figure five integer instructions can be executing simultaneously ...
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... MUL instruction eliminates the necessity of executing an explicit MFLO instruction. Also included in the RM5261 are the multiply-add instructions, MADU / MAD . This instruction multiplies two operands and adds the resulting product to the current contents of the Hi and Lo registers ...
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... Overlap of the divide/square root and multiply/add operations is supported. The RM5261 maintains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. Precise exceptions are extremely important in object-oriented programming environments and highly desirable for debugging in any environment. ...
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... In addition, the RM5261 includes registers to implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data error detection ...
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... This mechanism is available to system software to provide a secure environment for user processes. Bits in the CP0 register Status determine which virtual addressing mode is used. In the user mode, the RM5261 provides a single, uniform virtual address space of 1TB ( 32-bit mode). When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5TB ( 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address ...
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... TLB entry. The second mechanism controls the replacement algorithm when a TLB miss occurs. The RM5261 provides a random replacement algorithm to select a TLB entry to be written with a new mapping; however, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism allows the operating system to guarantee that certain pages are always mapped for performance Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’ ...
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... The non-coherent protocols are used for both code and data on the RM5261, with data using write- back or write-through depending on the application. The coherency attributes generate coherent transaction types on the system interface. However, in the RM5261 cache coherency is not supported. Hence the coherency attributes should never be used ...
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... Data Cache For fast, single cycle data access, the RM5261 includes on-chip data cache that is two- way set associative with a fixed 32-byte (eight words) line size. The data cache is protected with byte parity and its tag is protected with a single parity bit virtually indexed and physically tagged to allow simultaneous address translation and data cache access ...
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... In the event of a store immediately followed by a load to the same address, a combined merge and cache write occurs such that no penalty is incurred. The RM5261 cache attributes for both the instruction and data caches are summarized in Table 3. ...
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... System Address/Data Bus The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the RM5261 and the rest of the system protected with an 8-bit parity check bus (SysADC). The system interface is configurable to allow easy interfacing to memory and I/O systems of varying frequencies ...
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... Handshake Signals There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are used by an external device to indicate to the RM5261 whether it can accept a new read or write transaction. The RM5261 samples these signals before deasserting the address on read and write requests ...
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... If WrRdy* is deasserted during the issue phase of a write operation, the cycle is aborted by the processor and reissued at a later time. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Data0 Data1 Data2 ...
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... This capability eliminates the need to go through the normal software routine for exception decode and dispatch, thereby lowering interrupt latency. 3.29 Standby Mode The RM5261 provides a means to reduce the amount of power consumed by the internal core when the CPU would otherwise not be performing any useful operations. This state is known as Standby Mode. ...
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... Enable the timer interrupt on Int5* 1: Disable the timer interrupt on Int5* 12 Reserved: Must be zero Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Mode bit Description 14:13 Output driver strength - 100% = fastest ...
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... Pin Descriptions The following is a list of interface, interrupt, and miscellaneous pins available on the RM5261. Table 5 System Interface Pin Name Type ExtRqst* Input Release* Output RdRdy* Input WrRdy* Input ValidIn* Input ValidOut* Output SysAD[63:0] Input/Output SysADC[7:0] Input/Output SysCmd[8:0] Input/Output SysCmdP Input/Output Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ ...
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... JTMS Input Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Description System Clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation ...
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... Allows the system to change the processor addressing mode without rewriting the mode ROM. Vcc is OK When asserted, this signal indicates to the RM5261 that the 3.3V power supply has been above 3.0V for more than 100 milliseconds and will remain stable. The assertion of VccOK initiates the reading of the boot-time mode control serial stream ...
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... Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet 1 Limits –0 +85 – ...
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... VccP must be connected to VccInt through a passive filter circuit. See the RM5200 User’s Manual for the recommended filter circuit. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Vss VccInt VccIO ...
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... Minimum VccIO - 0. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Maximum Conditions 0.2V |I 0.4V |I 2.4V -0.3V 0.8V 2.0V VccIO + 0. Released |= 100 A ...
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... Worst case instruction mix with maximum supply voltage. 3. I/O supply power is application dependent, but typically <20% of VccInt. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet CPU Clock Speed 200 MHz 250 MHz 1 ...
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... ModeClock Period JTAG Clock Period Note 1. Operation of the RM5261 is only guaranteed with the Phase Lock Loop Enabled. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet ...
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... Only mode 14: tested and guaranteed. 9.4 Boot-Time Interface Parameters Parameter Mode Data Setup Mode Data Hold Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet 1 Conditions 5 mode14: (fastest) 5 mode14: ...
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... SysCmd, ValidIn*, ValidOut*, etc.) Figure 10 Input Timing SysClock Data Figure 11 Output Timing SysClock Data Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet t t High Low t t Fall Rise ...
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... D3 21.0 REF. E3 21.0 REF. L 0.46 0.56 e 0.50 BSC b 0.17 0.22 b1 0.17 0.20 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet 2.00 DIA 4 PLACES DA-B H 0. (E2 E1/2 “COUNTRY OF ORIGIN” MARK 4.00 R. 3.00 REF. DIA. 4 PLACES ...
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... A1 is defined as the distance from the seating plane to the lowest point of the package body. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Max Note Released ...
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... Vss 137 Vss 141 SysAD56 145 SysAD57 149 SysAD58 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Pin Function Pin SysAD4 7 10 VccInt ...
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... SysAD0 193 SysAD1 197 SysAD2 201 VccIO 205 NC Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Pin Function Pin 154 NC 155 158 NC 159 162 Vss ...
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... RM5261–250–Q RM5261–266–Q RM5261–200–QI (Contact Sales prior to design) Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet I Temperature Grade: (blank) = commercial I = Industrial ...