S29C51004B SyncMOS, S29C51004B Datasheet
S29C51004B
Related parts for S29C51004B
S29C51004B Summary of contents
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... The device also supports full chip erase. Boot block architecture enables the device to boot from a protected sector located either at the top (S29C51004T) or the bottom (S29C51004B). All inputs and outputs are CMOS and TTL compatible. The S29C51004T/S29C51004B is ideal for applications that require updatable code and data storage ...
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... A14 5 A17 6 32-Pin TSOP Standard Pinout A18 9 Top View 10 A16 A15 11 12 A12 S29C51004T/S29C51004B V1.0 May 2002 T – SPEED PKG PDIP 70: 70ns T = TSOP-I 90: 90ns J = PLCC 12: 120ns ...
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... Input Voltage with Respect to GND on I/O, address or control pins V Current CC NOTE: 1. Includes all pins except V . Test conditions Test Load Device Under Test C = 100 pF L S29C51004T/S29C51004B V1.0 May 2002 X-Decoder Control Logic I/O Buffer & Data Latches Test Setup OUT Min. ...
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... CC1 I Write Current CC2 I TTL Standby Current SB I CMOS Standby Current SB1 V Device ID Voltage for Device ID Current for S29C51004T/S29C51004B V1.0 May 2002 Commercial - +13 -0.5 to +5.5 -65 to +125 0 to +70 200 (Max.) Test Conditions Min Max ...
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... S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY -12 Max. Min. Max. Unit — 120 — — 120 ns 90 — 120 ns 45 — — ...
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... S29C51004T/S29C51004B V1.0 May 2002 OLZ t t CLZ OH VALID DATA OUT VALID DATA OUT WHWH1 (3) ( I/O OUT 7 6 S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY t DF HIGH-Z 51004- 51004-10 ...
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... WHWH1 ( I/O7 OUT 5555H 5555H 2AAAH t AH 55H 80H AAH 7 S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY 51004-11 (5555H for Chip Erase WHWH 3 (10H for Chip Erase) 55H 30H 51004-12 ...
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... OEH WE I/O I I/O -I/O I/O -I Waveforms of Toggle Bit Cycle CE t OEH WE OE I/O 6 S29C51004T/S29C51004B V1.0 May 2002 WHWH1 ( VALID DATA OUT I/O 7 INVALID VALID DATA OUT t WHWH1 ( S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY HIGH-Z HIGH-Z ...
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... The S29C51004 is available in two versions: the S29C51004T with the Boot Block address starting from 7C000H to 7FFFFH, and the S29C51004B with the Boot Block address starting from 00000H to 3FFFFH. Read Cycle A read cycle is performed by holding both CE and OE signals LOW ...
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... PD: The data at the byte address to be programmed. 5. SA(5): Sector Address Chip Erase Cycle The S29C51004T/S29C51004B features a chip- erase operation. The chip erase operation sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the chip erase command (see Table 2) ...
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... SyncMOS Technologies Inc. Boot Block Protection Status In Autoselect mode, performing a read at address location 3CXX2H (S29C51004T) or 0CXX2H (S29C51004B) will indicate boot bloc protection status. If the data is 01H, the boot block is protected. If the data is 00H, the boot block is unprotected. This is also shown is table 3. ...
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... Sequence 5555H/A0H PA/PD Data Polling or Toggle bit successfully completed or t timeout WTWH ( Writing Completed S29C51004T/S29C51004B V1.0 May 2002 S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Chip/Sector Erase Algorithm Write Erase Command Sequence Add/Data 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H 5555H/10H (Chip Erase) ...
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... DATA Polling Algorithm Read I/O 7 (1) Address = PBA No I/O = Data 7 Yes Program Done NOTE: 1. PBA: The byte address to be programmed. S29C51004T/S29C51004B V1.0 May 2002 S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Toggle Bit Algorithm Read I/O 6 Read I/O 6 Yes I/O Toggle 6 No Program Done 51004-17 13 ...
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... TYP .017 .420 .003 S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY 15 MAX .600 TYP +.004 – .0004 .136 .003 .046 .003 .025 ...
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... MAX. S29C51004T/S29C51004B V1.0 May 2002 0.787 0.008 0.010 0.315 TYP. (0.319 MAX.) SEATING PLANE 0.032 TYP. 0.020 MAX. 0.003 MAX 15 S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Detail “A” 0.024 0.004 0.035 0.002 0.047 MAX. 0.020 SBC 0.009 0.002 ...
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... Publication date : November 1998 Rev May 2002 Rev All data and specification are subject changed with Program (Erase/Program) Cycle as below description : a. Chip erase time : 2.0 sec → 3.0 sec maximum. b. Byte program time : 20 usec → 35 usec maximum S29C51004T/S29C51004B V1.0 May 2002 S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY 16 ...