SC1211 Semtech Corporation, SC1211 Datasheet - Page 9

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SC1211

Manufacturer Part Number
SC1211
Description
Combi-SenseTM Synchronous MOSFET Driver
Manufacturer
Semtech Corporation
Datasheet

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the DRN (or the Power Phase Node) with the same tim-
ing. A RC network (Rcs and Ccs) is connected between
VPN and Vout. During Q1 turn-on, Qcst turns on as well.
The voltage drop across Q1 and Lo charges Ccs. During
Q2 turn-on, Qcsb turns on as well. The voltage drop across
Q2 and Lo discharges Ccs. Both voltage drops are pro-
portional to the inductor current and a resistance equal
to FET’s Rdson plus ESR of the inductor. If the time con-
stant Rcs x Ccs is close to the Lo/Ro of the inductor,
where Ro is given by
the signal developed across Ccs will be proportional to
the inductor current, where Ro is the equivalent current
sensing resistance. In the above equation, Rinductor is
ESR of the inductor, Rdson_hs and Rdson_ls are the top
and bottom FET’s Rdson, and D is the duty cycle of the
converter.
Since a perfect timing match down to the nanosecond is
impossible, the VPN totem pole is held in tri-state during
the communtations of DRN in the SC1211. This avoids
errors and offset on the current detection which can be
significant since the timing mismatch is multiplied by the
input voltage. An optional capacitor between VPN and
DRN allows these two nodes to be AC coupled during
the tri-state window, hence yields a perfect timing match.
Refer to Semtech SC2643VX Combi-Sense
Mode Controller about the details of the Combi-Sense
technique.
Optimized Gate Drive Voltage
With the supply voltage in between 9V to 16V, an inter-
nal LDO is designed with the SC1211 to bring the volt-
age to a lower level for gate drive. An external Ceramic
capacitor(1uF to 4.7uF) connected in between Vreg to
ground is needed to support the LDO. The LDO output is
connected to low gate drive internally, and has to be
connected to high gate drive through an external boot-
strap circuit. The LDO output voltage is set at 8.5V. The
manufacture data and bench tested results show that,
for low R
mum gate drive voltage is around 8.5V, where the total
power losses of power FETs, including conduction loss
and switching loss, are minimized.
Ro
POWER MANAGEMENT
Applications Information (Cont.)
2003 Semtech Corp.
R
inductor
dson
FETs run at applied load current, the opti-
R
dson
_
hs
*
D
R
dson
_
ls
*
1 (
D
TM
)
Current
9
Thermal Shut Down
The SC1211 will shut down by pulling both driver out-
puts low if its junction temperature, T
COMPONENT SELECTION
Switching Frequency, Inductor and MOSFETs
The SC1211 is capable of providing up to 3.5A peak
drive current, and operating up to 1.5MHz PWM frequency
without causing thermal stress on the driver. The selec-
tion of switching frequency, together with inductor and
FETs is a trade-off between the cost, size, and thermal
management of a multi-phase voltage regulator. In mod-
ern microprocessor applications, these parameters could
be in the range of:
Switching Frequency 100kHz to 500kHz per phase
Inductor Value
FETs
Bootstrap Circuit
The SC1211 uses an external bootstrap circuit to pro-
vide a voltage for the top FET drive. This voltage, refer-
ring to the Phase Node, is held up by a bootstrap capaci-
tor. The capacitor value can be calculated based on the
total gate charge of the top FET, Q
voltage ripple on the capacitor, V
C
Typically, it is recommended to use a 1uF ceramic ca-
pacitor with 25V rating and a commonly available diode
IN4148 for the bootstrap circuit. In addition, a small re-
sistor (one ohm) has to be added in between DRN of the
SC1211 and the Phase Node. The resistor is used to
allievate the stress of the SC1211 from exposing to the
negative spike at the Phase node. A negative spike could
occur at the Phase Node during the top FET turn-off due
to parasitic inductance in the switching loop. The spike
could be minimized with a careful PCB layout. In those
applications with TO-220 package FETs, it is recom-
mended to use a clamping diode on the DRN pin to miti-
gate the impact of the excessive phase node negative
spike.
BST
> Q
TOP
/ V
BST
0.2uH to 2uH
4m-ohm to 20m-ohm R
20nC to 100nC total gate charge
BST
TOP
, in one PWM cycle:
j
, exceeds 155°C.
, and an allowed
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SC1211
dson

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