SC16C2550 Philips Semiconductors, SC16C2550 Datasheet - Page 19

• Manufacturer Part Number: SC16C2550
• Description: Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9397 750 11621
Product data
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
7.3.1 DMA mode
7.3 FIFO Control Register (FCR)
When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2550 in the FIFO
polled mode of operation. In this mode, interrupts are not generated and the user
must poll the LSR register for TX and/or RX data status. Since the receiver and
transmitter have separate bits in the LSR either or both can be used in the polled
mode by selecting respective transmit or receive control bit(s).
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
Mode 0 (FCR bit 3 = 0):
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) on
PLCC44 and LQFP48 packages will go to a logic 0 whenever the FIFO (THR, if FIFO
is not enabled) is empty. Receive Ready (RXRDY) on PLCC44 and LQFP48
packages will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded
with a character.
Mode 1 (FCR bit 3 = 1):
transmit interrupt is set when the transmit FIFO is empty. TXRDY on PLCC and
LQFP48 packages remains a logic 0 as long as one empty FIFO location is available.
The receive interrupt is set when the receive FIFO fills to the programmed trigger
level. However, the FIFO continues to fill regardless of the programmed level until the
FIFO is full. RXRDY on PLCC44 and LQFP48 packages transitions LOW when the
FIFO reaches the trigger level, and transitions HIGH when the FIFO empties.
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LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1-4] will provide the type of receive errors, or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
LSR[7] will show if any FIFO data errors occurred.
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
Rev. 03 — 19 June 2003
Set and enable the interrupt for each single transmit or
Set and enable the interrupt in a block mode operation. The
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C2550
encoder/decoder
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