SC16C2550 Philips Semiconductors, SC16C2550 Datasheet - Page 7

• Manufacturer Part Number: SC16C2550
• Description: Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 2:
9397 750 11621
Product data
Symbol
INTA,
INTB
IOR
IOW
OP2A,
OP2B
RESET
RXRDYA,
RXRDYB
TXRDYA,
TXRDYB
V
XTAL1
CC
Pin description
30, 29 33, 32
21
18
31, 13 35, 15
35
-
-
40
16
DIP40 PLCC44 LQFP48
24
20
39
34, 23
1, 12
44
18
Pin
…continued
30, 29
19
15
32, 9
36
31, 18
43, 6
42
13
Type Description
O
I
I
O
I
O
O
I
I
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
Interrupt A, B (3-State). This function is associated with individual channel
interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a
logic 1, interrupts are enabled in the interrupt enable register (IER), and is
active when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected.
Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load
the contents of an internal register defined by address bits A0-A2 onto the
SC16C2550 data bus (D0-D7) for access by external CPU.
Write strobe (Active-LOW strobe). A logic 0 transition on this pin will
transfer the contents of the data bus (D0-D7) from the external CPU to an
internal register that is defined by address bits A0-A2.
Output 2 (user-defined). This function is associated with individual
channels, A through B. The state at these pin(s) are defined by the user
and through MCR register bit 3. INTA, INTB are set to the active mode and
OP2 to logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the
3-State mode and OP2 to a logic 1 when MCR[3] is set to a logic 0. See
bit 3, Modem Control Register (MCR[3]). Since these bits control both the
INTA, INTB operation and OP2 outputs, only one function should be used
at one time, INT or OP2.
Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers
and all the outputs. The UART transmitter output and the receiver input will
be disabled during reset time. (See
reset condition”
Receive Ready A, B (Active-LOW). This function is associated with
PLCC44 and LQFP48 packages only. This function provides the
RX FIFO/RHR status for individual receive channels (A-B). RXRDYn is
primarily intended for monitoring DMA mode 1 transfers for the receive data
FIFOs. A logic 0 indicates there is a receive data to read/upload, i.e.,
receive ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the
programmed trigger level has not been reached. This signal can also be
used for single mode transfers (DMA mode 0).
Transmit Ready A, B (Active-LOW). This function is associated with
PLCC44 and LQFP48 packages only. These outputs provide the
TX FIFO/THR status for individual transmit channels (A-B). TXRDYn is
primarily intended for monitoring DMA mode 1 transfers for the transmit
data FIFOs. An individual channel’s TXRDYA, TXRDYB buffer ready status
is indicated by logic 0, i.e., at lease one location is empty and available in
the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are
no more empty locations in the FIFO or THR. This signal can also be used
for single mode transfers (DMA mode 0).
Power supply input.
Crystal or external clock input. Functions as a crystal input or as an
external clock input. A crystal can be connected between this pin and
XTAL2 to form an internal oscillator circuit. This configuration requires an
external 1 M resistor between the XTAL1 and XTAL2 pins. Alternatively,
an external clock can be connected to this pin to provide custom data rates.
(See
Rev. 03 — 19 June 2003
Section 6.8 “Programmable baud rate
for initialization details.)
Section 7.11 “SC16C2550 external
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
generator”.) See
SC16C2550
encoder/decoder
Figure
5.
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