SC16C750 Philips Semiconductors, SC16C750 Datasheet
SC16C750
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SC16C750 Summary of contents
Page 1
... On-board status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The SC16C750 operates 3.3 V and 2.5 V, the industrial temperature range and is available in plastic PLCC44 and LQFP64 packages. 2. Features ...
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... Baud generation ( Mbits/s) Loop-back controls for communications link fault isolation 10 +85 C. amb Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO Version SOT187-2 10 1.4 mm SOT314-2 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... LOGIC RECEIVE RECEIVE FIFO REGISTERS REGISTER FLOW CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 RCLK BAUDOUT Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO TX SHIFT RX SHIFT DTR RTS OUT1, OUT2 MODEM CONTROL LOGIC CTS RI DCD DSR 002aaa335 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Product data RCLK SC16C750IA44 CS0 CS1 15 CS2 16 BAUDOUT 17 Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO 39 RESET 38 OUT1 37 DTR 36 RTS 35 OUT2 INT 32 RXRDY 002aaa336 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... UART. The clock rate is established by the reference oscillator frequency divided by a divisor specified in the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to RCLK. Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO ...
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... Master Reset. I Master Reset. When active (HIGH), MR clears most UART registers and sets the levels of various output signals. Not connected. Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... I Serial data output composite serial data output to a connected communication device set to the marking (HIGH) level as a result of Master Reset. Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... IOW tied LOW or IOW tied HIGH). I Crystal connection or External clock input. O Crystal connection or the inversion of XTAL1 if XTAL1 is driven. Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... The SC16C750 is an upward solution that provides 64 bytes of transmit and receive FIFO memory, instead of none in the 16C450 the 16C550. The SC16C750 is designed to work with high speed modems and shared network environments that require fast data processing time ...
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... The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger level, but not the transmit trigger level. The SC16C750 provides independent trigger levels for both receiver and transmitter. To remain compatible with SC16C550, the transmit interrupt trigger level is set to 16 following a reset ...
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... Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS logic 1. If CTS transitions from a logic logic 1 indicating a flow control request, the SC16C750 will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS input returns to a logic 0, indicating more data may be sent ...
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... Fig 4. Crystal oscillator connection. The generator divides the input 16 clock by any divisor from SC16C750 divides the basic crystal or external clock by 16. The frequency of the BAUDOUT output pin is exactly 16 (16 times) of the selected baud rate (BAUDOUT = 16 Baud Rate). Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator ...
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... DMA operation The SC16C750 FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output pins ...
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... RX, RI, CTS, DSR, DCD transmit data is provided by the user. If the sleep mode is enabled and the SC16C750 is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user ...
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... FLOW CONTROL LOGIC MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 RCLK BAUDOUT Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO TX RX RTS DSR DTR CTS OUT1 RI OUT2 DCD 002aaa337 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... The Special Register set is accessible only when LCR[7] is set to a logic 1. [4] Enhanced Feature Register is accessible only when LCR is set to ‘BF 9397 750 11623 Product data details the assigned bit functions for the fifteen SC16C750 internal registers. Bit 7 Bit 6 Bit 5 Bit 4 ...
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... FIFO full; logic least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register (RHR). Receive data is removed from the SC16C750 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate ...
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... FIFO reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C750 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s) ...
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... Logic 0 = Set DMA mode ‘0’ (normal default condition). Logic 1 = Set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC16C750 is in the 16C450 mode (FIFOs disabled; FCR[0] = logic the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0 ...
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... FIFO Control Register bits description Symbol Description Transmit operation in mode ‘1’: When the SC16C750 is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 when the trigger level has been reached. ...
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... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C750 provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... Logic 0 or cleared = default condition. LCR[1-0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Logic 0 or cleared = default condition. Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO Table 15). Table 16). Table 17). © ...
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... Word length Stop bit length (bit times LCR[1-0] word length LCR[0] Word length Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Logic 0 = Force DTR output to a logic 1 (normal default condition). Logic 1 = Force DTR output to a logic 0. Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO SC16C750 I/O pins. Figure 5). In this mode, the receiver © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C750 and the CPU. Table 19: Bit 9397 750 11623 Product data Line Status Register bits description Symbol Description LSR[7] FIFO data error. Logic error (normal default condition). ...
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... A modem Status Interrupt will be generated. [1] MSR[2] RI Logic change (normal default condition). Logic 1 = The RI input to the SC16C750 has changed from a logic logic 1. A modem Status Interrupt will be generated. Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO … ...
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... Bit 1 0 [1] Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C750 provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Table 21: Bit 7 ...
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... Philips Semiconductors 7.11 SC16C750 external reset conditions Table 22: Register IER ISR LCR MCR LSR MSR FCR EFR Table 23: Output TX RTS DTR RXRDY TXRDY INT 8. Limiting values Table 24: In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg ...
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... (databus (other outputs 800 A 1.85 OH (databus 400 A 1.85 OH (other outputs [2] 500 for a listing of pins having internal pull-up resistors. Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO 3.3 V 5.0 V Max Min Max Min Max 0.45 0.3 0.6 0.5 0.6 V 2 0.65 0.3 0.8 0.5 0 ...
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... Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO 3.3 V 5.0 V Unit Min Max Min Max MHz ...
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... VALID ADDRESS t 6h VALID ACTIVE t 11d t 11d ACTIVE t t 12d 12h DATA Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO 2.5 V 3.3 V 5.0 V Max Min Max Min Max clock cycle. ...
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... DATA VALID t 7h ACTIVE ACTIVE t 12h t 12d DATA Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO 002aaa332 VALID ADDRESS ACTIVE t t 12d 12h 002aaa333 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... ACTIVE t t 13w 15d ACTIVE t 16h t 16s DATA t 17d CHANGE OF STATE CHANGE OF STATE t 18d ACTIVE ACTIVE Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO VALID ADDRESS ACTIVE t 13w t t 16s 16h 002aaa334 CHANGE OF STATE t 18d ACTIVE ACTIVE t ...
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... Product data DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO 002aaa112 NEXT DATA START PARITY STOP BIT BIT BIT 20d ACTIVE t 21d ...
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... Fig 14. Receive ready timing in FIFO mode. 9397 750 11623 Product data DATA BITS (5– DATA BITS (5– Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO NEXT DATA PARITY STOP START BIT BIT BIT 25d ACTIVE DATA READY t ...
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... Product data DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO NEXT DATA PARITY STOP START BIT BIT BIT 24d ACTIVE 002aaa116 © ...
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... Fig 16. Transmit ready timing in non-FIFO mode. 9397 750 11623 Product data DATA BITS (5– TRANSMITTER READY t 27d ACTIVE Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO NEXT DATA PARITY STOP START BIT BIT BIT 28d TRANSMITTER ...
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... Product data DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t 28d FIFO FULL Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO PARITY STOP BIT BIT D6 D7 002aaa118 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO SOT187 detail X (1) ( max. ...
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... 2 scale (1) ( 0.18 10.1 10.1 12.15 12.15 0.5 1 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO SOT314 detail X (1) ( 0.75 1.45 1.45 7 0.2 0.12 0.1 o 0.45 1.05 1.05 0 EUROPEAN ...
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... Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 9397 750 11623 Product data 2.5 mm thick/large packages. Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO 3 350 mm so called 3 so called small/thin packages. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , [5] , SO, SOJ Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO Soldering method Wave Reflow not suitable suitable [4] not suitable suitable ...
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... Product data (9397 750 10149); ECN 853-2367 28865 of 04 September 2002. 9397 750 11623 Product data 10 C measured in the atmosphere of the reflow 12: changed capacitors’ values and Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Rev. 04 — 20 June 2003 SC16C750 UART with 64-byte FIFO Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Scratchpad Register (SPR 7.10 Enhanced Feature Register (EFR 7.11 SC16C750 external reset conditions . . . . . . . 28 © Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice ...