SC16C752BIBS Philips Semiconductors, SC16C752BIBS Datasheet
SC16C752BIBS
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SC16C752BIBS Summary of contents
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SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Rev. 03 — 14 December 2004 1. Description The SC16C752B is a dual universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, ...
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... Package Name Description SC16C752BIB48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 SC16C752BIBS HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 9397 750 14443 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... Philips Semiconductors 4. Block diagram SC16C752B D0–D7 DATA BUS IOR AND IOW CONTROL LOGIC RESET A0–A2 REGISTER CSA SELECT CSB LOGIC INTA, INTB INTERRUPT TXRDYA , TXRDYB CONTROL RXRDYA , RXRDYB LOGIC Fig 1. Block diagram. 9397 750 14443 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... RXB RXA 5 6 TXRDYB SC16C752BIB48 TXA 7 TXB 8 OPB 9 CSA 10 CSB 11 n.c. 12 terminal 1 index area RXB 3 RXA 4 SC16C752BIBS TXA 5 (top view) TXB 6 OPB 7 CSA 8 Rev. 03 — 14 December 2004 SC16C752B 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OPA 31 RXRDYA 30 INTA 29 INTB ...
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... Philips Semiconductors 5.2 Pin description Table 2: Pin description Pin Symbol LQFP48 HVQFN32 CDA, CDB 40 CSA, CSB 10 CTSA, 38, 23 25, 16 CTSB D0-D4, 44-48, 27-31, 32, D5-D7 1-3 1-2 DSRA, 39 DSRB DTRA, 34 DTRB GND 17 13 INTA, INTB 30, 29 21, 20 IOR 19 14 IOW ...
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... Philips Semiconductors Table 2: Pin description …continued Pin Symbol LQFP48 HVQFN32 OPA, OPB 32, 9 22, 7 RESET 36 24 RIA, RIB 41 RTSA, 33, 22 23, 15 RTSB RXA, RXB RXRDYA, 31 RXRDYB TXA, TXB TXRDYA, 43 TXRDYB XTAL1 13 10 ...
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... Philips Semiconductors 6. Functional description The SC16C752B UART is pin-compatible with the SC16C2550 UART. It provides more enhanced features. All additional features are provided through a special enhanced feature register. The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor ...
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... Philips Semiconductors UART 1 RX FIFO FIFO Fig 4. Autoflow control (Auto-RTS and Auto-CTS) example. 6.2.1 Auto-RTS Auto-RTS data flow control originates in the receiver block (see diagram.” on page trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0] ...
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... Philips Semiconductors 6.2.2 Auto-CTS The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host system. When fl ...
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... Philips Semiconductors There are two other enhanced features relating to software flow control: • Xon Any function (MCR[5]): Operation will resume after receiving any character after recognizing the Xoff character possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO. • ...
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... Philips Semiconductors 6.3.3 Software flow control example Fig 7. Software flow control example. Assumptions: using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR[3: set to 60, and Xon threshold (TCR[7: set to 32. Both have the interrupt receive threshold (TLR[7: set to 52. ...
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... Philips Semiconductors 6.4 Reset Table 4 Table 4: Register Interrupt enable register Interrupt identification register FIFO control register Line control register Modem control register Line status register Modem status register Enhanced feature register Receiver holding register Transmitter holding register Transmission control register Trigger level register ...
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... Philips Semiconductors 6.5 Interrupts The SC16C752B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0-3, 5-7. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5 ...
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... Philips Semiconductors 6.5.1 Interrupt mode operation In interrupt mode (if any bit of IER[3: the processor is informed of the status of the receiver and transmitter by an interrupt signal, INT. Therefore not necessary to continuously poll the line status register (LSR) to see if any interrupt needs to be serviced. ...
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... Philips Semiconductors 6.6 DMA operation There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[ DMA occurs in single character transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the processor for longer periods of time. ...
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... Philips Semiconductors 6.6.2 Block DMA transfers (DMA mode 1) Figure 11 wrptr trigger level wrptr Fig 11. TXRDY and RXRDY in DMA mode 1. Transmitter: available. It becomes inactive when the FIFO is full. Receiver: a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR[7]. ...
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... Philips Semiconductors 6.8 Break and time-out conditions An RX idle condition is detected when the receiver line, RX, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the TX line is pulled LOW. A break condition is activated by setting LCR[6]. ...
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... Philips Semiconductors Table 7: Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Table 8: Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 ...
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... Philips Semiconductors Fig 13. Crystal oscillator connections. 7. Register descriptions Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table Table ...
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... Philips Semiconductors Table 10 Table 10: SC16C752B internal registers Shaded bits are only accessible when EFR[4] is set Register Bit 7 Bit 6 [1] General Register Set RHR bit 7 bit THR bit 7 bit IER 0/CTS 0/RTS interrupt interrupt [2] enable enable ...
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... Philips Semiconductors [3] The Special Register set is accessible only when LCR[7] is set to a logic 1. [4] Enhanced Feature Register; Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF Remark: Refer to the notes under 7.1 Receiver holding register (RHR) The receiver section consists of the receiver holding register (RHR) and the receiver shift register (RSR) ...
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... Philips Semiconductors 7.3 FIFO control register (FCR) This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11: Bit 7:6 5 9397 750 14443 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 11 shows FIFO control register bit settings ...
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... Philips Semiconductors 7.4 Line control register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12 Table 12: Bit 1:0 9397 750 14443 Product data ...
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... Philips Semiconductors 7.5 Line status register (LSR) Table 13 Table 13: Bit When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is output directly onto the output data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identifi ...
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... Philips Semiconductors Remark: The three error bits (parity, framing, break) may not be updated correctly in the first read of the LSR when the input clock (XTAL1) is running faster than 36 MHz. However, the second read is always correct strongly recommended that when using this device with a clock faster than 36 MHz, that the LSR be read twice and only the second read be used for decision making ...
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... Philips Semiconductors 7.7 Modem status register (MSR) This 8-bit register provides information about the current state of the control lines from the mode, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. register bit settings per channel. ...
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... Philips Semiconductors Table 16: Bit [1] IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[ write enable. Re-enabling IER[1] will not cause a new interrupt if the THR is below the threshold. 7.9 Interrupt identification register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner ...
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... Philips Semiconductors Table 18: Priority level 7.10 Enhanced feature register (EFR) This 8-bit register enables or disables the enhanced features of the UART. shows the enhanced feature register bit settings. Table 19: Bit 3:0 9397 750 14443 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... Philips Semiconductors 7.11 Divisor latches (DLL, DLH) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores the least significant part of the divisor. ...
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... Philips Semiconductors 7.14 FIFO ready register The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels. Table 22: Bit 7 3 The FIFO Rdy register is a read-only register that can be accessed when any of the two UARTs is selected CSA or CSB = 0, MCR[2] (FIFO Rdy Enable logic 1, and loop-back is disabled ...
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... Philips Semiconductors 8. Programmer’s guide The base set of registers that is used during high-speed data transfer have a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access ...
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... Philips Semiconductors Table 23: Command Set TX FIFO and RX FIFO thresholds to VALUE Read FIFO Rdy register Set prescaler value to divide-by-1 Set prescaler value to divide-by-4 [1] sign here means bit-AND. 9397 750 14443 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Register programming guide … ...
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... Philips Semiconductors 9. Limiting values Table 24: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T operating ambient temperature amb T storage temperature stg [1] Stresses beyond those listed under Limiting values may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “ ...
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... Philips Semiconductors [3] These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 C. The customer is responsible for verifying junction temperature. [4] These parameters apply for D7-D0. [5] These parameters apply for DTRA, DTRB, INIA, INTB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB. [6] Measurement condition, normal operation other than sleep mode 3.3 V ...
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... Philips Semiconductors Table 26: AC electrical characteristics + 2.5 V, 3.3 V amb CC Symbol Parameter clock cycle period clock speed p3 t RESET pulse width (RESET) t address set-up time su1 t data set-up time su2 t set-up time from IOW or IOR assertion su3 to XTAL1 clock LOW-to-HIGH transition ...
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... Philips Semiconductors VALID A0–A2 ADDRESS t su1 CSA, CSB t d5 IOW D0–D7 Fig 15. General write timing. IOW IOR t su3 XTAL1 Fig 16. Alternate read/write strobe timing. 9397 750 14443 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs t h4 ACTIVE t h2 ...
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... Philips Semiconductors active IOW RTSA, RTSB change of state DTRA, DTRB CDA, CDB CTSA, CTSB DSRA, DSRB INTA, INTB IOR RIA, RIB Fig 17. Modem input/output timing. RXA, RXB INTA, INTB IOR Fig 18. Receive timing. 9397 750 14443 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... Philips Semiconductors START BIT RXA RXB RXRDYA RXRDYB IOR Fig 19. Receive ready timing in non-FIFO mode. START BIT RXA RXB RXRDYA RXRDYB IOR Fig 20. Receive ready timing in FIFO mode. 9397 750 14443 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... Philips Semiconductors TXA, TXB INTA, INTB active IOW Fig 21. Transmit timing. START BIT TXA, TXB ACTIVE IOW D0–D7 BYTE #1 TXRDYA, TXRDYB Fig 22. Transmit ready timing in non-FIFO mode. 9397 750 14443 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... Philips Semiconductors START BIT TXA, TXB ACTIVE IOW D0–D7 BYTE #32 t d17 TXRDYA, TXRDYB Fig 23. Transmit ready timing in FIFO mode. 9397 750 14443 Product data 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs DATA BITS (5- DATA BITS ...
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... Philips Semiconductors 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 0.27 1.6 mm 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... Philips Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A (1) UNIT max. 0.05 0.30 5 0.2 0.00 0.18 4.9 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Philips Semiconductors 13. Soldering 13.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fi ...
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... CWQCCN..L For more detailed information on the BGA packages refer to the (LF)BGA Application Note [1] (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26 ...
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... Philips Semiconductors [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C oven. The package body peak temperature must be kept as low as possible. ...
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... Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. ...
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... Philips Semiconductors Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 7 6.1 Trigger levels 6.2 Hardware flow control . . . . . . . . . . . . . . . . . . . . 7 6.2.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 Software flow control . . . . . . . . . . . . . . . . . . . . 9 6.3.1 RX 6.3 6.3.3 Software flow control example . . . . . . . . . . . . 11 6.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.5.1 Interrupt mode operation . . . . . . . . . . . . . . . . 14 6 ...