LV24230LS Sanyo Semicon Device, LV24230LS Datasheet
LV24230LS
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LV24230LS Summary of contents
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... The LV24230LS C-controlled single-chip FM tuner IC that integrates external components which are necessary for tuning in a compact VQLP package with dimensions of only 3.5×3.5×0.85mm LV24230LS has the capability to perform automatic tuning/seek and dissipates less power than conventional LV24000series tuner ICs. Features • ...
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... Interface block allowable operation range -20 to +70° Parameter Supply voltage Digital block input Digital block output External clock operating frequency Note : External clock input (pin 12) allows also input of the sine wave signal. LV24230LS Symbol Conditions V CC Analog block supply voltage V DD Digital block supply voltage ...
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... Package Dimensions unit : mm (typ) 3393 TOP VIEW SIDE VIEW 3.5 SIDE VIEW Pin Assignment LV24230LS BOTTOM VIEW (0.1) 0. (0.75) 0.2 SANYO : VQLP24J(3.5X3. Line_out_L 19 Package-GND 20 21 Package-GND Package-GND 22 23 Package-GND 24 GND Ext_CLK_IN 12 11 Package-GND 10 Package-GND 9 Package-GND 8 Package-GND 7 SCL 6 No ...
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... Block Diagram Line_out_L 19 Package_GND 20 Package_GND 21 Package_GND 22 Package_GND 23 24 GND To Each Block LV24230LS Line SW Buffer And AMP Mute FM Stereo Demodulator Decorder FM Selectivity Filter FLL Tuning RF and FM Quadrature Quadrature Oscillator Mixer To Each Block Voltage 12 Ext_CLK_IN Stabilizer To Each Block ...
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... LINE-OUT-R 19 LINE-OUT-L 20 Package-GND 21 Package-GND 22 Package-GND 23 Package-GND 24 GND LV24230LS Description Pin voltage Antenna input 1V Antenna GND 1V Digital interface supply voltage Digital supply voltage Interrupt line Digital interface DATA ine) Digital interface Clock line) GND for package-shield GND for package-shield GND for package-shield ...
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... Eight data bits are sent from LV24230LS to the master while Ack is sent from the master to LV24230LS. SCL D7 SDA The serial clock SCL is supplied from the master side essential that data bit is output from LV24230LS in synchronization with the falling edge while the master side performs latching at the rising edge. LV24230LS 2 ...
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... Interrupt Pin INT LV24230LS has the dedicated interrupt output pin. For the active level to the host, either LOW or HIGH can be selected. The INT output pin is kept floating while the PWRAD bit is cleared during initialization. Therefore, to avoid influence on the CPU side during initialization recommended to secure the non-active state by means of the pull-up or pull-down resistor ...
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... Set-up time of STOP condition Set-up time of Data Bus free time between a STOP and Capacitivie load for each bus line *Cb = Total capacitance of one bus line (2). Register map (On Register Map) Following is Sub address map of LV24230LS. Each register becomes 8-bit constitution. Address Register Name 00h CHIP_ID 02h ...
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... Register description (ON Contents of each Register) Register 00h – CHIP_ID – Chip identify register (Read/Write bit 7 8-bit chip ID. LV24230LS : 12h Note : To abort the command, write any value in this register. Register 02h – RADIO_STAT – Radio station status (Read-Only RAD_IF ...
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... Soft audio mute level 1 100b = Soft audio mute level 2 (*) Note : do not use without these value. (*) : recommended setting bit 1 : Reserved : 0 (Fix) bit 0 : STABI_BP : Internal regulator by-pass bit 0 = Internal regulator operate (normal Internal regulator by-pass LV24230LS AGC_SPD DEEM ST_M SOFTMU [ ...
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... PW_RAD : Radio Circuit Power 0 = Power Off (Stand-by Power On Note : At the time of start, PW_RAD becomes 0 (Stand-by) Register 10h – TNPL – Tune position low (Read-Only bit 7-0 : TUNEPOS [ Current RF Frequency (Low 8bit) LV24230LS RAD_IE SD_PM nIF_PM Reference clock Off 32768Hz crystal oscillator ...
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... Divider Value = Divider Value = 2 … 255 : Divider Value = 256 Register 1Bh –REF_CLK_OFF – Reference clock offset (Read/Write Bit 7-0 : REFOFFS [ Offset register for the spread of reference clock LV24230LS SM_IF TUNED Remark OK, Command end (No Error) Default value after or during reset ...
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... Target value of oscillator calibration, Tuning frequency value or limit frequency value for station search Note : GRID [ not 0 TARGET [15 : 14] has different definition With radio power ON, lower eight bits of the target frequency are set. Then, set higher eight bits of the target frequency to this register. The command is executed. LV24230LS ...
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... Test Circuit Line_out_R Line_out_L 1.0μF FM_ANT R:50Ω VIO Voltage SW Source SW LV24230LS 1.0μ Top View 22 Package GND 23 GND 1000pF 1000pF 0.1μ Voltage Source 22μF 0.1μ External_CLK_IN Voltage 12 Source Package GND 8 Pull-up SCL R:2.2kΩ ...
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... C bus communication line requires pull-up resistors R5 and R6. The commonly-employed resistance value is 2.2k. Set the pull-up voltage to the same one of VIO of LV24230LS. (Supply from the same source as VIO and recommended. Note6 : Please use the INT pin arbitrarily. Recommended to open when unused. ...
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... PCB Mounting Conditions to cover the FM Receiving Area of 76M to 108MHz Printed Circuit Board • LV24230LS has an inductor for local oscillator on the package bottom side. In order to cover the receiving frequency range of 76MHz to 108MHz, provide the GND layer to the first layer of Side A of PCB that is directly below the package bottom side, as shown in the figure. ...
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... SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2011. Specifications and information herein are subject to change without notice. LV24230LS PS No.A1989-17/17 Datasheet pdf - http://www.DataSheet4U.net/ ...