MX25L1605ZM Macronix International, MX25L1605ZM Datasheet
MX25L1605ZM
Related parts for MX25L1605ZM
MX25L1605ZM Summary of contents
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... Minimum 10K erase/program cycle for array • Minimum 100K erase/program cycle for additional 4Kb SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Auto Erase and Auto Program Algorithm P/N: PM1291 MX25L1605ZM Macronix NBit 16M-BIT [x 1] CMOS SERIAL eLiteFlash - Automatically erases and verifies data at selected sector - ...
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... HOLD#(2) WP#/ACC VCC GND PO0~PO6 NC Note: HOLD# is recommended to connect to VCC during parallel mode. 2 MX25L1605ZM DESCRIPTION Chip Select Serial Data Input output/input Clock Input Hold, to pause the serial communication (HOLD# is not for parallel mode) Write Protection: connect to GND; 12V for program/erase acceleration: connect to 12V + 3 ...
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... BLOCK DIAGRAM www.DataSheet4U.com SI CS#, ACC, WP#,HOLD# SCLK P/N: PM1291 MX25L1605ZM Address Generator Memory Array Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 3 Output Sense Buffer Amplifier SO REV. 1.0, MAY 16, 2006 ...
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... Release from Deep Powerdown instruction). P/N: PM1291 MX25L1605ZM • To avoid unexpected changes by system power supply transition, the Power-On Reset and an internal timer (tPUW) can protect the device. • Before the Program, Erase, and Write Status Register execution, instruction length will be checked on follow- ing the clock pulse number to be multiple of eight base ...
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... The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. P/N: PM1291 Protection Area BP0 16Mb 0 None 1 Upper 32nd (Sector 31) 0 Upper sixteenth (two sectors: 30 and 31) 1 Upper eighth (four sectors 31) 0 Upper quarter (eight sectors 31) 1 Upper half (sixteen sectors 31) 0 All 1 All 5 MX25L1605ZM REV. 1.0, MAY 16, 2006 ...
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... AND PROGRAM PERFORMACE". Figure 2. ACCELERATED PROGRAM TIMING DIAGRAM V HH 12V ACC Note: tVHH (VHH Rise and Fall Time) min. 250ns P/N: PM1291 Hold Condition (standard use VHH 6 MX25L1605ZM Hold Condition (non-standard use VHH REV. 1.0, MAY 16, 2006 ...
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... Erase) Program) Power 4Kb Down) sector Hex B9 Hex A5 Hex AD1 AD2 AD3 Enter the additional additional 4Kb sector 7 MX25L1605ZM WRSR READ Fast Read Parallel register) data) 01 Hex 03 Hex 0B Hex AD1 AD1 AD2 AD2 AD3 AD3 x to write new ...
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... Address Range 31 1F0000h 30 1E0000h 29 1D0000h 28 1C0000h 27 1B0000h 26 1A0000h 25 190000h www.DataSheet4U.com 24 180000h 23 170000h 22 160000h 21 150000h 20 140000h 19 130000h 18 120000h 17 110000h 16 100000h P/N: PM1291 MX25L1605ZM Sector 1FFFFFh 15 1EFFFFh 14 1DFFFFh 13 1CFFFFh 12 1BFFFFh 11 1AFFFFh 10 19FFFFh 9 18FFFFh 8 17FFFFh 7 16FFFFh 6 15FFFFh 5 14FFFFh 4 13FFFFh 3 12FFFFh 2 11FFFFh 1 10FFFFh 0 8 Address Range ...
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... During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. P/N: PM1291 SCLK SCLK SI MSB SO 9 MX25L1605ZM MSB REV. 1.0, MAY 16, 2006 ...
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... RDID operation can use CS# to high at any time during data out. (see Figure. 14) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1291 MX25L1605ZM 10 REV. 1.0, MAY 16, 2006 ...
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... SRWD Status Program/ Register Write erase Protect error 1= status register write 1=error disable Note: 1. See the table "Protected Area Sizes". P/N: PM1291 MX25L1605ZM bit 5 bit 4 bit 3 BP2 BP1 0 the level of the level of the level of protected protected protected block block (note 1) (note 1) ...
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... When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0 software protected mode (SPM) P/N: PM1291 MX25L1605ZM Write Protection of the Status Register ...
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... Figure 29~34) b. For normal write command (by SI), No effect c. Under parallel mode, the fastest access clock freq. will be changed to 1.5MHz(SCLK pin clock freq.) d. For parallel mode, the tAA will be change to 50ns. P/N: PM1291 MX25L1605ZM TM Memory will be in parallel mode until VCC power-off ...
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... Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. P/N: PM1291 MX25L1605ZM 14 REV. 1.0, MAY 16, 2006 ...
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... RDID instruction. Even in Deep power-down mode, the RDP, RES, and REMS are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. The sequence is shown as Figure 23,24,25. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if P/N: PM1291 MX25L1605ZM 15 REV. 1.0, MAY 16, 2006 ...
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... Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions: RDID Command RES Command REMS Command P/N: PM1291 manufacturer ID memory type C2 20 manufacturer MX25L1605ZM memory density 15 electronic ID 14 device ID 14 REV. 1.0, MAY 16, 2006 ...
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... POWER-ON STATE www.DataSheet4U.com P/N: PM1291 MX25L1605ZM 17 REV. 1.0, MAY 16, 2006 ...
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... During voltage transitions, all pins may overshoot to -0.5V to 4.6V 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V -0.5V to 4.6V while VCC+0.5V is smaller than or equal to 4.6V. Figure 5. Maximum Positive Overshoot Waveform 20ns 4.6V 3.6V MIN. TYP 18 MX25L1605ZM 20ns MAX. UNIT CONDITIONS 10 pF VIN = VOUT = 0V REV. 1.0, MAY 16, 2006 ...
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... Figure 7. OUTPUT LOADING P/N: PM1291 Input timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns DEVICE UNDER TEST CL 6.2K ohm CL=30pF Including jig capacitance 19 MX25L1605ZM Output timing referance level 0.5VCC 2.7K ohm +3.3V DIODES=IN3064 OR EQUIVALENT REV. 1.0, MAY 16, 2006 ...
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... VOL Output Low Voltage VOH Output High Voltage NOTES: 1. Typical values at VCC = 3.3V These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation. P/N: PM1291 MX25L1605ZM for Commercial grade, VCC = 2.7V ~ 3.6V) NOTES MIN. TYP MAX ...
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... Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 3. P/N: PM1291 MX25L1605ZM for Commercial grade, VCC = 2.7V ~ 3.6V) Serial Serial Parallel Serial ...
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... Note: 1. These parameters are characterized only. www.DataSheet4U.com INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1291 MX25L1605ZM Min. Max 1.5 ...
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... Figure 8. Serial Input Timing CS# tCHSL SCLK www.DataSheet4U.com SI SO Figure 9. Write Protect Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS# SCLK SI SO P/N: PM1291 tSLCH tDVCH tCHDX MSB IN High Impedance High Impedance 23 MX25L1605ZM tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN tSHWL REV. 1.0, MAY 16, 2006 ...
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... Figure 10. Hold Timing CS# SCLK www.DataSheet4U.com SO SI HOLD# Figure 11. Output Timing CS# SCLK tCLQV tCLQX SO ADDR.LSB IN SI P/N: PM1291 tHLCH tCHHL tCHHH tHLQZ tCLQV tCLQX 24 MX25L1605ZM tHHCH tHHQX tCH tCL tSHQZ LSB OUT tQLQH tQHQL REV. 1.0, MAY 16, 2006 ...
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... SO CS SCLK Instruction SI High Impedance Instruction Manufacturer Identification High Impedance MSB 25 MX25L1605ZM Device Identification MSB REV. 1.0, MAY 16, 2006 ...
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... SCLK Instruction SI High Impedance Instruction 24-Bit Address MSB High Impedance 26 MX25L1605ZM Status Register Out MSB Status Register ...
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... BIT ADDRESS High Impedance Dummy Byte DATA OUT MSB 27 MX25L1605ZM DATA OUT MSB MSB REV. 1.0, MAY 16, 2006 ...
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... Data Byte MSB MSB Instruction 23 22 MSB 28 MX25L1605ZM Data Byte MSB Data Byte 256 ...
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... Instruction Instruction 3 Dummy Bytes MSB X 29 MX25L1605ZM Stand-by Mode Deep Power-down Mode RES2 Electronic Signature Out MSB Deep Power-down Mode REV ...
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... High Impedance ADD ( Manufacturer MSB 30 MX25L1605ZM t RES1 Stand-by Mode Device MSB MSB REV. 1.0, MAY 16, 2006 ...
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... Figure 26. Power-up Timing (max (min) www.DataSheet4U.com V WI P/N: PM1291 Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed tVSL Reset State of the Device tPUW 31 MX25L1605ZM Read Access allowed Device fully accessible time REV. 1.0, MAY 16, 2006 ...
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... Bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. Any new write command will clear this bit. P/N: PM1291 CS SCLK Instruction SI High Impedance SO CS SCLK Instruction SI High Impedance SO 32 MX25L1605ZM 7 7 REV. 1.0, MAY 16, 2006 ...
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... To read array in parallel mode requires a parallel mode command (55H) before the read command. Once in the parallel mode, eLiteFlash 8. In READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. P/N: PM1291 MX25L1605ZM TM Memory will not exit parallel mode until power-off. 33 REV. 1.0, MAY 16, 2006 ...
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... Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.). 7. To program in parallel mode requires a parallel mode command (55H) before the program command. Once in the parallel mode, eLiteFlash P/N: PM1291 MX25L1605ZM TM Memory will not exit parallel mode until power-off. 34 ...
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... In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec. P/N: PM1291 Instruction Manufacturer Identification High Impedance X Byte output Device Identification TM Memory will not exit parallel mode until power-off. 35 MX25L1605ZM High Impedance REV. 1.0, MAY 16, 2006 ...
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... P/N: PM1291 Instruction 3 Dummy Bytes Memory will not exit parallel mode until power-off. 36 MX25L1605ZM RES2 0 Electronic Signature Out X Byte Output Deep Power-down Mode Stand-by Mode REV. 1.0, MAY 16, 2006 ...
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... Once in the parallel mode, eLiteFlash 8. In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec. P/N: PM1291 MX25L1605ZM TM Memory will not exit parallel mode until power-off. 37 ...
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... Instruction 2 Dummy Bytes High Impedance ADD ( Manufacturer ID X Device ID TM Memory will not exit parallel mode until power-off. 38 MX25L1605ZM REV. 1.0, MAY 16, 2006 ...
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... VCC Rise Time Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1291 MX25L1605ZM tCHSL tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up ...
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... Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1291 Min. TYP 2.4 Main Array 10K Additional 4Kb 100K 40 MX25L1605ZM Max. (2) UNIT Comments Note ( Note (4) 2.4 s Note ( Note (4) ...
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... ORDERING INFORMATION PART NO. MX25L1605ZMC-20G MX25L1605ZMI-20G www.DataSheet4U.com P/N: PM1291 ACCESS OPERATING STANDBY TIME(ns) CURRENT(mA) CURRENT(uA MX25L1605ZM Temperature PACKAGE 50 0~70 C 8-land SON 50 -40~85 C 8-land SON REV. 1.0, MAY 16, 2006 Remark Pb-free Pb-free ...
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... PART NAME DESCRIPTION MX 25 www.DataSheet4U.com P/N: PM1291 L 1605 OPTION: G: Pb-free blank: normal SPEED: 20: 50MHz, for SPI TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: ZM: SON DENSITY & MODE: 1605: 16Mb TYPE DEVICE: 25: Serial Flash 42 MX25L1605ZM REV. 1.0, MAY 16, 2006 ...
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... PACKAGE INFORMATION www.DataSheet4U.com P/N: PM1291 MX25L1605ZM 43 REV. 1.0, MAY 16, 2006 ...
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... MX25L1605ZM MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...