MX25L3205A Macronix International, MX25L3205A Datasheet
MX25L3205A
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MX25L3205A Summary of contents
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... Minimum 10K erase/program cycle for array • Minimum 100K erase/program cycle for additional 4Kb SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Auto Erase and Auto Program Algorithm P/N: PM1243 MX25L3205A Macronix NBit 32M-BIT [x 1] CMOS SERIAL eLiteFlash - Automatically erases and verifies data at selected sector - ...
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... GENERAL DESCRIPTION The MX25L3205A is a CMOS 33,554,432 bit serial TM eLiteFlash Memory, which is configured as 4,194,304 x 8 internally. The MX25L3205A features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO) ...
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... BLOCK DIAGRAM Address Generator SI CS#, ACC, WP#,HOLD# SCLK P/N: PM1243 Memory Array Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 3 MX25L3205A www.DataSheet4U.com Output Sense Buffer Amplifier SO REV. 1.2, NOV. 06, 2006 ...
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... DATA PROTECTION The MX25L3205A are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...
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... The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. P/N: PM1243 Protection Area 32Mb None Upper 64th (Sector 63) Upper 32nd (two sectors: 62 and 63) Upper sixteenth (four sectors 63) Upper eighth (eight sectors 63) Upper quarter (sixteen sectors 63) Upper half (thirty-two sectors 63) All 5 MX25L3205A www.DataSheet4U.com REV. 1.2, NOV. 06, 2006 ...
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... AND PROGRAM PERFORMACE". Figure 2. ACCELERATED PROGRAM TIMING DIAGRAM V HH 12V ACC t VHH Note: tVHH (VHH Rise and Fall Time) min. 250ns P/N: PM1243 MX25L3205A Hold Hold Condition Condition (standard) (non-standard) 6 www.DataSheet4U.com VHH ...
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... Deep Down) sector) sector) Power-down) B9 Hex A5 Hex B5 Hex AB Hex Enter Exit the the additional additional 4Kb 4Kb sector sector 7 MX25L3205A www.DataSheet4U.com READ Fast Read Parallel Mode data) 03 Hex 0B Hex 55 Hex AD1 AD1 AD2 AD2 AD3 AD3 x n bytes Enter and ...
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... MX25L3205A www.DataSheet4U.com Address Range 1F0000h 1FFFFFh 1E0000h 1EFFFFh 1D0000h 1DFFFFh 1C0000h 1CFFFFh 1B0000h 1BFFFFh 1A0000h 1AFFFFh 190000h 19FFFFh 180000h 18FFFFh 170000h 17FFFFh 160000h 16FFFFh 150000h 15FFFFh 140000h 14FFFFh ...
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... Note: CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported. P/N: PM1243 MX25L3205A shift in MSB 9 www.DataSheet4U.com ...
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... The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte followings: 16(hex) for MX25L3205A. The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> ...
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... SRWD Status Program/ 0 Register Write erase Protect error 1= status register write 1=error disable Note: 1. see the table "Protected Area Sizes" P/N: PM1243 MX25L3205A bit 4 bit 3 bit 2 BP2 BP1 BP0 the level of the level of the level of protected protected protected block block block (note 1) ...
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... When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0 software protected mode (SPM) P/N: PM1243 MX25L3205A www.DataSheet4U.com WP# and SRWD bit status ...
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... For normal write command (by SI), No effect c. Under parallel mode, the fastest access clock freq. will be changed to 1.5MHz(SCLK pin clock freq.) d. For parallel mode, the tAA will be change to 50ns. P/N: PM1243 TM Memory will be in parallel mode until VCC power-off. 13 MX25L3205A www.DataSheet4U.com REV. 1.2, NOV. 06, 2006 TM ...
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... Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. P/N: PM1243 MX25L3205A www.DataSheet4U.com 14 REV. 1.2, NOV. 06, 2006 ...
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... The sequence is shown as Figure 23,24,25. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if P/N: PM1243 MX25L3205A www.DataSheet4U.com 15 REV. 1.2, NOV. 06, 2006 ...
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... Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions: RDID Command manufacturer ID C2 RES Command REMS Command P/N: PM1243 memory type 20 electronic ID 15 manufacturer MX25L3205A www.DataSheet4U.com memory density 16 device ID 15 REV. 1.2, NOV. 06, 2006 ...
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... At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. P/N: PM1243 MX25L3205A www.DataSheet4U.com 17 REV. 1.2, NOV. 06, 2006 ...
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... During voltage transitions, all pins may overshoot to -0.5V to 4.6V 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V -0.5V to 4.6V while VCC+0.5V is smaller than or equal to 4.6V. Figure 5. Maximum Positive Overshoot Waveform 4.6V 3.6V MIN. TYP 18 MX25L3205A www.DataSheet4U.com 20ns MAX. UNIT CONDITIONS 10 pF VIN = VOUT = 0V ...
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... Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level 0.8VCC 0.2VCC Figure 7. OUTPUT LOADING DEVICE UNDER TEST P/N: PM1243 MX25L3205A Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns 2.7K ohm CL 6.2K ohm DIODES=IN3064 ...
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... VOL Output Low Voltage VOH Output High Voltage NOTES: 1. Typical values at VCC = 3.3V These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation. P/N: PM1243 MX25L3205A for Commercial grade, VCC = 2.7V ~ 3.6V) MIN. TYP MAX. UNITS ...
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... Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 3. P/N: PM1243 MX25L3205A for Commercial grade, VCC = 2.7V ~ 3.6V) Serial Serial Parallel Serial ...
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... Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1243 MX25L3205A www.DataSheet4U.com Min. Max ...
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... Figure 8. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 9. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1243 MX25L3205A tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tCL tQLQH tQHQL 23 www.DataSheet4U.com tSHSL tSHCH tCHCL tSHQZ LSB REV. 1.2, NOV. 06, 2006 ...
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... SI is "don't care" during HOLD operation. Figure 11. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO P/N: PM1243 tHLCH tCHHL tCHHH tHLQZ MX25L3205A www.DataSheet4U.com tHHCH tHHQX tSHWL REV. 1.2, NOV. 06, 2006 ...
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... P/N: PM1243 Command 06 High Command 04 High Manufacturer Identification MSB MSB 25 MX25L3205A www.DataSheet4U.com Device Identification REV. 1.2, NOV. 06, 2006 ...
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... Register MSB High 24-Bit Address MSB X 7 MSB 26 MX25L3205A www.DataSheet4U.com Status Register Out MSB Data Out 1 Data Out ...
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... BIT ADDRESS DATA OUT MSB MSB 27 MX25L3205A www.DataSheet4U.com DATA OUT MSB REV. 1.2, NOV. 06, 2006 ...
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... MSB Command 24 Bit Address MSB 28 MX25L3205A www.DataSheet4U.com Data Byte Data Byte 256 MSB REV. 1.2, NOV. 06, 2006 ...
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... DP Command B9 Stand-by Mode Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode 29 MX25L3205A www.DataSheet4U.com Deep Power-down Mode Sequence t RES2 Stand-by Mode REV. 1.2, NOV. 06, 2006 ...
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... Dummy Bytes Manufacturer MSB MSB 30 MX25L3205A www.DataSheet4U.com Stand-by Mode 47 Device MSB REV. 1.2, NOV. 06, 2006 ...
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... Figure 26. Power-up Timing (max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed V CC (min) Reset State of the Flash V WI P/N: PM1243 MX25L3205A www.DataSheet4U.com tVSL Read Command is Device is fully allowed accessible tPUW 31 time REV. 1.2, NOV. 06, 2006 ...
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... Note 1: Chip erase and WRSR will not be executed in 4kbit mode Note 2: Chip erase can't erase this 4kbit About the fail status: Bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. Any new write command will clear this bit. P/N: PM1243 MX25L3205A ...
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... To read array in parallel mode requires a parallel mode command (55H) before the read command. Once in the parallel mode, eLiteFlash 8. In READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. P/N: PM1243 MX25L3205A TM Memory will not exit parallel mode until power-off. 33 www.DataSheet4U.com ...
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... Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.). 7. To program in parallel mode requires a parallel mode command (55H) before the program command. Once in the parallel mode, eLiteFlash P/N: PM1243 MX25L3205A TM Memory will not exit parallel mode until power-off. 34 www ...
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... In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec. P/N: PM1243 Manufacturer Identification High-Z X Byte output Device Identification TM Memory will not exit parallel mode until power-off. 35 MX25L3205A www.DataSheet4U.com REV. 1.2, NOV. 06, 2006 ...
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... P/N: PM1243 Dummy Bytes Electronic Signature Out X Byte Output Deep Power-down Mode TM Memory will not exit parallel mode until power-off. 36 MX25L3205A www.DataSheet4U.com RES2 Stand-by Mode REV. 1.2, NOV. 06, 2006 ...
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... Once in the parallel mode, eLiteFlash 8. In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec. P/N: PM1243 MX25L3205A TM Memory will not exit parallel mode until power-off. 37 www ...
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... P/N: PM1243 Dummy Bytes ADD ( Manufacturer ID X Device ID TM Memory will not exit parallel mode until power-off. 38 MX25L3205A www.DataSheet4U.com 47 REV. 1.2, NOV. 06, 2006 ...
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... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1243 tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 39 MX25L3205A www.DataSheet4U.com tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 0.5 ...
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... Input Voltage with respect to GND on ACC Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1243 MX25L3205A Min. TYP. (1) Max. (2) UNIT 64 128 ...
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... ORDERING INFORMATION PART NO. ACCESS TIME(ns) MX25L3205AMC-20 20 MX25L3205AMC-20G 20 MX25L3205AMI-20 20 MX25L3205AMI-20G 20 MX25L3205AZMC-20G 20 MX25L3205AZMI-20G 20 P/N: PM1243 MX25L3205A OPERATING STANDBY Temperature PACKAGE CURRENT(mA) CURRENT(uA www.DataSheet4U.com Remark 0~70 C 16-SOP 0~70 C 16-SOP Pb-free -40~85 C 16-SOP -40~85 C 16-SOP Pb-free 0~70 C 8-SON Pb-free -40~85 C 8-SON Pb-free REV. 1.2, NOV. 06, 2006 ...
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... PART NAME DESCRIPTION 3205A P/N: PM1243 MX25L3205A OPTION: G: Pb-free blank: normal SPEED: 20: 50MHz, for SPI TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: M: 300mil 16-SOP ZM: 8-SON DENSITY & MODE: 3205A: 32Mb TYPE DEVICE: 25: Serial Flash 42 www ...
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... PACKAGE INFORMATION P/N: PM1243 MX25L3205A www.DataSheet4U.com 43 REV. 1.2, NOV. 06, 2006 ...
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... P/N: PM1243 MX25L3205A www.DataSheet4U.com 44 REV. 1.2, NOV. 06, 2006 ...
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... REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" title 1.1 1. Format change 1.2 1. Added statement P/N: PM1243 MX25L3205A www.DataSheet4U.com Page P1 All P46 45 Date OCT/13/2005 JUN/08/2006 NOV/06/2006 REV. 1.2, NOV. 06, 2006 ...
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... Macronix's products in the prohibited applications ACRONIX NTERNATIONAL Headquarters Macronix America, Inc. Macronix Japan Cayman Islands Ltd. Macronix (Hong Kong) Co., Limited. http : //www.macronix.com MX25L3205A C L O., TD. Taipei Office Macronix Europe N.V. Singapore Office MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 46 ...