TM121XG_02L02D TORiSAN, TM121XG_02L02D Datasheet - Page 8

• Manufacturer Part Number: TM121XG_02L02D
• Description: LCD_Module
• Manufacturer: TORiSAN

RCLK +/-
Rin1 +/-
Rin2 +/-
Rin0 +/-
Tottori SANYO Electric Co., Ltd.
[Note 1] "DE mode" only.
[Note 2] INTERFACE SIGNALS are loaded from LVDS-transmitter to TFT Timing generator
INTERFACE (LVDS) DATA ASSIGNMENT
INTERFACE SIGNALS
DCLK
HSYNC
VSYNC
DE
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
SYMBOL
The valid synchronous signals are DCLK and DE. HSYNC and VSYNC are invalid.
with LVDS sequence. (See BLOCK DIAGRAM.)
Data Clock
Horizontal Sync - This signal initiates a new line (negative).
Vertical Sync
Data Enable
Red Data
Red Data
Red Data
Red Data
Red Data
Red Data
Green Data
Green Data
Green Data
Green Data
Green Data
Green Data
Blue Data
Blue Data
Blue Data
Blue Data
Blue Data
Blue Data
G0(LSB)
Rxout 6
Rxout13
Rxout20
DE
B1
R5(MSB)
B0(LSB)
Rxout12
Rxout19
Rxout 5
VSYNC
(LSB)
(MSB)
(LSB)
(MSB)
(LSB)
(MSB)
(positive)
- This signal initiates a new frame (negative).
G5(MSB)
Rxout11
Rxout18
HSYNC
Rxout 4
R4
TM121XG-02L02D Ver.2
B5(MSB)
FUNCTION
Rxout10
Rxout17
Rxout 3
R3
G4
Rxout16
Rxout 2
Rxout 9
G3
R2
B4
Rxout15
Rxout 1
Rxout 8
G2
R1
B3
R0(LSB)
Rxout14
Rxout 0
Rxout 7
Page
G1
B2
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