TM121XG_02L02D TORiSAN, TM121XG_02L02D Datasheet - Page 9

• Manufacturer Part Number: TM121XG_02L02D
• Description: LCD_Module
• Manufacturer: TORiSAN

Tottori SANYO Electric Co., Ltd.
[Note 1] In the following timing waveform, the n-th edge of internal imaginary clock tcn,
[Note 1] Please confirm tcj2 (Jitter rate), only if tcj1 (P-P of jitter/100cycles) exceeds 300ps.
[Additional explanation]
P-P of jitter / 100 cycles
Jitter rate
Data Setup Time
Data Hold Time
INTERFACE (LVDS) SIGNAL TIMING PARAMETERS
CYCLE JITTER of LVDS CLOCK
CYCLE JITTER of LVDS CLOCK.
15.0ns and tCLK MAX. is 15.42ns between
0nc and 100nc. The tcj1 (P-P of jitter / 100
cycles) in this sphere is
and out of specification (300ps MAX.).
So, it is neccesary to measure tcj2 (jitter rate)
and to judge whether it conform to above
specification.
fluctuation of tCLK is 0.4ns per 5nc. So that,
the tcj2 in this sphere is
and larger than specification (20ps/cycle MAX.).
In conclusion, normal function of the LCD module can not be assured in this case.
PARAMETER
PARAMETER
Right diagram shows the example of
According to this diagram, tCLK MIN. is
tcj1=15.42-15.0=0.42 ns
According to the diagram, the sharpest
tcj2=0.4/5=0.08 ns/cycle
where Tin is period of LVDS input clock.
For this imaginary clock edge, data setup time is tsu and data hold time is thd,
respectively.
which is sampling position of LVDS input data signal, is given by:
LVDS Input Clock
LVDS Input Data
tcn = (2n-1) Tin / 14
SYMBOL
SYMBOL
n-th edge of internal imaginary clock (data sampling position)
tcj1
tcj2
tsu
thd
MIN
MIN
600
600
tcn
-
-
(n=1,2, ~ 7)
TM121XG-02L02D Ver.2
tsu
Tin
thd
TYP
TYP
-
-
-
-
15.6
15.5
15.4
15.3
15.2
15.1
15.0
14.9
MAX
MAX
300
20
-
-
0
CYCLE JITTER of LVDS CLOCK
ps/cycle
50
UNIT
UNIT
ps
ps
ps
Cycle
<EXAMPLE>
100
at Tin=15ns
Note 1
Note 1
n
c (n)
150
NOTE
NOTE
Page
200
8/16
250